Customer Testimonial - Packet Engines  

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"I’ve never had a problem taking a Virtex FPGA and getting the performance I need out of it, says Tom Trosta, ASIC Design Engineer at Packet Engines.   "What I would say is from an FPGA perspective with the range of gate counts and IO sizes that the part offers me I see no reason to use anything other than Virtex."

Packet Engines

Packet Engine’s charter is to develop the next generation carrier class IP packet over switch router.  That is a router that will include OC3 through OC192 compliant interfaces.  It is marketed toward border routers and core routers for ISP backbones for companies such as AT&T, MCI and AOL.  It’s a market that is projected to grow to 20 thousand units per year in shipments at its peak.  The ASIC role within that product is to implement wire speed routing in the computer architecture.  And that is done with about 8 separate ASICs.  The current ASIC that I am running is implemented in a Virtex XCV600 piece of silicon and its function is to serve as the power PC bridge to the rest of the system.  We have a power PC 750 class processor that runs through our Virtex bridge chip to a PCI local bus double data rate DRAM interface and a high speed serial backplane.  It’s about 500k gates and we run at a frequency of 50 to 100 MHz.  To put the processing in perspective, this classic system is about 20% more powerful then the Pentium II processor you might find on your desk.  The switch is architected to include 10 to 50 of these subsystems in the final product. 

We went with Virtex in this particular design quite simply because it met all the functional needs we had and it met them at the performance requirements that we needed.  I have estimated that, per my schedule, by going to Virtex I saved 4 months off of the design cycle.  Where that becomes significant in this type of product is it is associated with a software staff of about 50 engineers.  So a four month design cycle save has 50 engineers working on actual hardware 4 months faster than it could with a standard cell implementation. So, in the grand scheme of a full product cycle, it is very significant to reduce risk under a model like that.  I have used FPGAs really since they started.  I remember using the Xilinx 2000 series parts back 10 years ago.  They have served their traditional role as ASIC prototypes in final designs for that elusive type of technology.  But I think what we are seeing with Virtex now is surprising everybody: they can actually get to a million gates; run them at system frequencies of 50, 75, even 100 MHz; and these traditional roles where they were serving as maybe an FPGA prototype, now gets into first production release type silicon and under many conditions will be the ultimate silicon in the product.  So, for me, watching from the early days of the 2000 series parts to now with Virtex, it’s exciting to see where it is going and I’m looking forward to seeing what the next generation of Virtex parts look like. 

I think what Virtex has done is taken FPGAs out of their role as a glue logic, a popcorn logic type device, and it has actually made them a system level tool.  In addition to the IO capacity of them, we’ve got integrated memory now and in densities of hundreds of thousands of bits, where before as systems designs we would have to take that memory off-chip.  By taking it off-chip, we typically take a performance hit in doing that.  By keeping it on-chip we are running very high-speed FIFOs now and very high-speed dual port memories and system performance is going up as we keep functions on the chip.  The IO diversities are really important.  A lot of times we have to go off-chip with translators to accomplish that.  Now we get that on-chip.  In general, I think what we have really done here is we have created devices that before were running in the tens of megahertz range and now have grown them up to 50 MHz and beyond into system level designs like we are here.  It lets us change the complexion of how we design systems now.  From a scalability perspective it was always a hit in the programmable logic arena where if you started with a 10,000 gate device and migrated up to a 50,000 gate device you took a penalty in operational performance, your frequency typically went down.   I’ve taken Virtex parts and ran them in 300 series parts and run them up to 1000 series parts and kept a frequency of 50MHz throughout that whole range.  Not everybody in this market space can say that, but Virtex does and can. 

We’ve developed quite a few ASICs at Packet Engines.  I think what you’ll see is that there used to be a transfer where the FPGAs were typically done by the board level designers, and as such they were schematic capture based systems where someone was pounding out based on a schematic capture environment.  We’ve gone to hundreds of thousands of gates of logic now and as such we are designing ASIC and we’re not doing schematic capture based logic design anymore.  So what we are seeing in the industry, in my opinion, is our ASIC designs now designing the logic that is going into the FPGAs. I’ve never had a problem taking a Virtex type FPGA and getting the performance I need out of it.  And what I would say is from an FPGA perspective with the range of gate counts and IO sizes that the part offers me I see no reason to use anything other than Virtex for that space.  Then in the isolated condition that I would go to a standard cell it has to be when I need ultra high performance in the 150 MHz range or some special and unique mixed mode type signal that I would need.  So from a standardization perspective, Xilinx is positioned very well with Virtex. 

For more information on Packet Engines, visit their web site at http://www.ind.alcatel.com. 
 

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