A thru H |
Definition of Terms
|
Agent |
An Agent is any initiator/target on the PCI bus. |
Burst Transaction |
Any transaction consisting of more than one data phase |
Doubleword |
32 bits, most often known as "DWORD" |
I thru P |
![Q-Z](../rp0000a/rp00a23.gif)
|
ISA |
Industry Standard Architecture (ISA) is a standard bus (computer interconnection)
architecture that is associated with the IBM AT motherboard. It allows
16 bits at a time to flow between the motherboard circuitry and an expansion
slot card and its associated device(s). |
Local Bus |
The "local bus" is the physical path on which data flows at almost
the speed of the microprocessor, and increases the total system performance. |
Master |
The Master or Initiator owns the bus and initiates the data transfer.
Each Initiator must also be a target. |
PCI SIG |
The PCI Special Interest Group (SIG) is an unincorporated association
of members of the microcomputer industry set up for the purpose of monitoring
and enhancing the development of the PCI architecture. The SIG is led by
a nine member steering committee and governed by SIG bylaws. |
PCI |
PCI stands for Peripheral Component Interconnect. The PCI Local Bus
is a high-performance bus that provides a processor independent data path
between the CPU and high-speed peripherals. PCI is a robust interconnect
mechanism designed specifically to accommodate multiple high performance
peripherals for graphics, full motion video, SCSI, LAN, etc. |
Q thru Z |
![More Info](../rp0000a/rp00a23.gif)
|
Quadword |
64 bits, sometimes knows as "QWORD" |
Slave (or Target) |
The Slave (or Target) is the target on the PCI bus. |
Turnaround cycle |
The turnaround cycle is a "dead" bus cycle to prevent bus contention. |
VESA |
VESA (Video Electronics Standards Association) Local Bus (sometimes
called the VESA VL bus) is a standard interface between your computer and
its expansion slots that provides faster data flow between the devices
controlled by the expansion cards and your computer's microprocessor. |
Wait State |
The wait state is a bus cycle where it is possible to transfer data,
but no data transfer occurs. |