The Xilinx Programmable Logic Training Courses

Who Should Attend a Training Course?

All users of Xilinx products should attend one of our training courses. Attending a Xilinx training course is one of the fastest and most efficient ways to learn how to design with FPGA devices from Xilinx. Hands-on expert instruction with the latest information and software will allow you to implement your own designs in less time with more effective use of the devices.

Classes are held regularly in centers around the world and can even be brought to your own facility.

Not only design engineers, but also test engineers, component engineers, CAD engineers, technicians, and engineering managers may want to attend the course in order to understand the Xilinx products.

What You Will Learn

Not only will you learn about our products, but we will also recommend the best ways to use the software based on our years of experience with thousands of designs. You will learn how to efficiently enter, implement, and verify your design. You can use the Xilinx automatic mode or take a power-user approach and guide the automatic tools to the best implementation of your design.

Prerequisites

Students need only have a background in digital logic design. Basic familiarity with the PC or workstation is helpful but not required. It will benefit you to learn your design entry tool of choice before attending the Xilinx course.

If you would like to prepare for the training course to maximize your learning, you should complete the tutorials available in the development system. There are tutorials available for the third-party tools for which Xilinx sells the interface.

Benefits

Make Fewer Design Iterations
By learning the proper approach, you will save time and expense in prototyping and debugging designs. However, if you do need to make changes to your design, you will learn how to do this quickly and efficiently.

Get to Market Faster
Getting your product to market faster is probably one of the key reasons you are using Xilinx products in the first place. Studies have shown that time-to-market often has a greater effect on profits than development costs. Training will allow you to get your product to market on schedule, allowing your company to reap the rewards that follow.

Reduce Your Learning Time
Extensive Xilinx documentation and tutorials provide the information you need to complete your design. But attending the training course for focused, interactive learning is faster than a question-and-answer approach on your own. Instead of interruptions and piecemeal self-education, you will quickly become your company's expert in Xilinx designs.

Lower Production Costs
By learning how to use the device effectively, you may be able to get more logic into a smaller device, and/or operate at a higher speed. As a result, you may be able to save on the cost of the device itself and the surrounding logic on your board.

Increase Quality
Effective verification techniques will prove the quality of your Xilinx-based design. Higher quality leads to less maintenance and repair costs, and improved customer satisfaction.

Time and Cost Savings

Attending a Xilinx training course is an investment that will pay for itself with the first Xilinx design that you begin. The courses are fast-paced, each providing as much information as possible in the short time available. Hands-on experiences throughout the courses make sure that the information is retained and applied to practical applications. Just as Xilinx products reduce your development time, attending a training course can reduce your design time. The person attending the course will be an in-house expert who can be utilized by other members of your company.

You can reduce your travel costs by attending a class scheduled in your area or having the course brought right to your facility. The tuition pays for the course notes and expert, in-person instruction, which can be priceless when trying to meet a schedule.

Course Descriptions

Hands-On Experience

Each course includes hands-on labs. There is at least one computer for every two people in the class.

Platforms

The courses use PC platforms with either WIN95 or NT operating systems.

Instructors

Xilinx training courses have been successfully held worldwide for over eight years. The instructors are Xilinx experts who are skilled at passing that knowledge on to fellow engineers. A dedicated Customer Education organization at Xilinx works closely with the Applications and Engineering groups to keep the courses up-to-date with the latest improvements to Xilinx and third-party tools.

Course Materials

All course materials are supplied by Xilinx. Every student gets an excellent reference tool in the form of course notes, which include all the material presented during the course. The course notes are bound for easy use and include additional reference material beyond what is covered in the course.

Product Coverage

Xilinx courses will cover the latest released versions of our devices and development systems. While all available products will be covered, emphasis will be placed on the more popular and/or recommended solutions. New products are added to the courses as they become available. If you have any questions on coverage of a particular product, please call the Xilinx Customer Education department.

Xilinx Courses

	Course Title	Course Length
	FPGA Tools	2 days
	Foundation Interface	1 day
	Foundation Express	1 day
	Getting Started With Xilinx FPGAs v2.1i	2 day
	VHDL Methodology	3 days
	Verilog Methodology	3 days
	PCI Core Basics	1 day
	PCI Core - Designing a PCI System	2 days
	Beginning Test Bench	2 days
	2.1 Update	1/2 day
	Virtex for XC4000 Series Users	1 day
	Essential VHDL and Synthesis for Xilinx FPGA Technology	2 days

FPGA Tools Course v1.5i

This Xilinx training course is two days in length. It is designed to be an introduction to the Xilinx products and tools for those customers who have little or no experience with the Xilinx environment. All North American training sites and most international locations teach this same course. The FPGA Tools course is heavily focused on the labs, which feature Xilinx’ Foundation Software.

FPGA Tools Course Outline

The following topics will be discussed during the Tools course:

Day 1
Course Introduction
Basic FPGA Architecture
Design Entry
LogiBLOX GUI and Core Generator
LogiBLOX Lab
Design Manager and Flow Engine
General Design Flow Lab
Report Browser
Timing
Basic Constraints
Timing Analyzer
Basic Timing Constraints Lab
On-line Documentation
Day 2
Hardware Optimization
Floorplanner Layout Lab
Advanced Timing Constraints
Advanced Constraints Lab
Implementation Options
Advanced PAR Options
Advanced Optimization Features Lab
EPIC

Foundation Interface Course v1.5i

The one-day Foundation Schematic Entry course will provide customers with the knowledge to fully utilize the tools capabilities. The tool contains a schematic editor, HDL editor, state editor, and a simulator that are tightly integrated with the M1 Implementation tools. The course is heavily focused on the labs. Each lab individually addresses a specific piece of the tool and its use in effectively designing an FPGA.

Foundation Interface Course Outline

The one-day Foundation course addresses the following topics:

Foundation Introduction
Basic FPGA Architecture and Libraries
Project Manager
Schematic Editor and Lab
LogiBLOX and Lab
HDL Editor and Lab
State Editor and Lab
Simulator and Lab
Advanced Simulator Usage and Lab

Foundation Express Course v1.5i

This one-day course is an introduction to Foundation using Foundation Express. The attendee will learn how to enter a design and create an optimized FPGA; the design will be verified in silicon. Customers should have a basic understanding of VHDL or Verilog before attending this course. This course supports both VHDL and Verilog

Foundation Express Course Outline

The agenda for the Foundation Express course is as follows:

Design Entry: Foundation tools for easy design entry
        Design Wizard
        Language Assistant
        LogiBLOX
Lab
Synthesis and Implementation
        Push-button Design Flow
        Analyzing the Design Performance
Lab
Constraining the Design
        Methods for Constraining Synthesis and Implementation
        Pin Locking, Control of I/O, Timing Constraints
HDL Coding Styles
        Design Tips for Small, Fast Designs (VHDL & Verilog)
Advanced Implementation Options (Optional-Time Dependent)
       Software Techniques for Implementation of Designs
           with Tight Timing Constraints

Xilinx Tools Update - v2.1i Course

Location	Aug.	Sept.	Oct.	Nov.	Dec.
San Jose, CA - Xilinx, Inc.	31		12

This half day course will give customers an introduction to the 2.1 Implementation Tools, 2.1 Foundation Tools, and the 2.1 Foundation Express Tools. The primary functionality of the tool sets will not be covered. Only the changes and new features to the tools from the 1.5 release will covered.

Prerequisites:

It is important for customers to have significant familiarity with the tool sets, because this is
not a new user class. Completion of the FPGA Tools, Foundation Interface, and the Foundation Express courses is also sufficient experience.

Course Outline:

Design Manager Improvements
Timing Analyzer Improvements
FPGA Editor
The New Constraints Editor Layout
Improvements for Virtex
Foundation Project Manager Improvements
Foundation Express Improvements
Express Schematic Viewer
     Viewing a Synthesized Design
     Time Tracker
     Delay Filters
     Tracing Paths
Demonstration
Questions and Answers
Demonstrations
Chance to Play with the Tools

Getting Started with Xilinx FPGAs v2.1i

Location	Aug.	Sept.	Oct.	Nov.	Dec.
San Jose, CA - Xilinx, Inc.	12-13	14-15	26-27

This course was developed specifically to help new users learn how to design successfully with Xilinx devices. During this 2 day course, the Foundation software implementation tool will be used to introduce new users to the essentials of designing with Xilinx FPGAs. Using our latest released software students will learn the basic FPGA architecture, designing techniques, and how to implement an FPGA design.

Prerequisites:

Basic knowledge of an HDL language is recommended.

Course Outline:

Day 1
Virtex Architecture
Xilinx Tool Flow
Lab - Xilinx Tool Flow
Reading Reports
Schematic Design Entry
FPGA Design
HDL Coding Tips
Lab - HDL Coding

Day 2
Global Timing Constraints
Introduction to the Timing Analyzer
Lab - Timing Constraints
Core Generator
Implementation Options
Viewing Your Design With the Floorplanner
Lab - Implementation Options
FPGA Configuration
Board Layout
Help Resources

FPGA Synthesis Methodology Workshops

These comprehensive courses are an effective introduction to the VHDL and Verilog languages with particular emphasis on targeting Xilinx and FPGA devices in general. The information gained here can be applied to any digital design using a Top-Down synthesis design approach. These courses are a combination of insightful lecture, coupled with practical and interesting lab exercises to reinforce the key concepts.

They are a great way to quickly gain proficiency in one of today's fastest growing hardware design techniques

VHDL Methodology Course Outline

The following topics will be discussed during the VHDL Methodology course:

Day 1
Introduction to VHDL & Hardware Modeling
Language Concepts
Signals & Datatypes
Operators / Expressions
Concurrent & Sequential Statements
Lab Exercises:
    Write Entities
    Build Hierarchical Structures with Instantiation
Day 2
Advanced Process Statements
Behavioral to RTL
VHDL Timing Models
Targeting Xilinx
Lab Exercises:
    Write Code for 4 State State-Machine
    Build One Hot Encoded State-Machine
Day 3
Introduction to the VHDL Testbench
Functions / Procedures
Xilinx Synthesis Tools
Lab Exercises:
    Build Testbench for Module Verification
    Download & In-circuit Verification of Synthesized Design

Verilog Methodology Workshop Outline

The Verilog Methodology workshop includes the following topics:

Day 1
Verilog HDL Introduction
Hardware Modeling Overview
Language Concepts
Verilog Modules & Ports
Gate Level Modeling
Operators & Expressions
Lab Exercises:
     Write Basic Modules
     Write Gate Level Model
     Build Hierarchical Structures with Instantiation
Day 2
Data-Flow Modeling
Behavioral Modeling
Advanced Process Statements
Verilog Timing Models
Targeting Xilinx
Lab Exercises:
     Write Behavioral Model
     Write & Compile 4 State-Machine
Day 3
Introduction to the Verilog Testbench
Tasks & Functions
Xilinx Synthesis Tools
Lab Exercises:
     Build Complex Address Decoder
     Download & In-circuit Verification of Synthesized Design

Xilinx PCI Core Basics

Location	Aug.	Sept.	Oct.	Nov.	Dec.
Xilinx - San Jose, CA		1	6		1

This PCI training course will give Xilinx customers an introduction to the basic PCI
concepts and architectures. It will also give a general presentation of Xilinx PCI solutions
and includes a lab showing the design flow from core configuration to verification.

Who should attend?

The audience should include Xilinx customers that have purchased Xilinx PCI products or
those who have Xilinx design experience and are interested to learn more about PCI.

Prerequisites

Students need to have the following:
       Some knowledge of PCI is recommended
       Working experience with digital design
       Basic knowledge of Verilog or VHDL
       Some experience of Xilinx Foundation and FPGA Express

Course Objective

After completing this course, students will be able to accomplish the following:
        Describe the basics of the PCI specification
        Select the appropriate PCI solution for a specific application
        Understand the basic design flow using Xilinx PCI

Xilinx PCI Core - Designing a PCI System

Location	Aug	Sept	Oct	Nov	Dec
Xilinx - San Jose, CA		2-3	7-8		2-3

Course Description

This PCI training course will give Xilinx customers a good understanding on how to use Xilinx PCI products. The student will learn the basics of Xilinx PCI cores, including PCI64/66 Virtex, PCI32
Spartan/Spartan XL, and PCI32 4000, and available PCI Bridge Designs. Moreover the student will learn design concepts and basic verification strategies for a PCI system design. The class includes labs where the student gets hands on experience using the Xilinx PCI cores with Foundation Express 1.5i, Synopsys FPGA Express, and Model Technology simulator.

Who should attend?

The audience should include Xilinx customers that have purchased Xilinx PCI products or those who have Xilinx design experience and good knowledge of PCI.

Prerequisites

Students need to have the following:
      Passed Xilinx PCI - basic PCI concepts or have good knowledge of PCI
      Working experience with digital design
      Basic knowledge of Verilog or VHDL
      Working experience of Xilinx Foundation and FPGA Express including writing UCF files

Course Objective

After completing this course, students will be able to accomplish the
following:

successfully complete a Xilinx PCI design, including configuration, implementation and verification, using available product documentation

Virtex for XC4000 Series Users

Location	Aug	Sept	Oct	Nov	Dec
Xilinx - San Jose, CA	16	30	18	16	14

This one-day training course is intended to teach Xilinx XC4000 users how to design effectively for Virtex. The focus will be on utilizing the Virtex architectural resources and obtaining optimum device utilization and design performance. The hands-on experience will include how to design for Virtex using a variety of synthesis tools. Specific applications will be identified that can utilize the Virtex architectural resources more effectively than the XC4000 device resources. There is also one lab in which students will synthesize and implement a high performance SDRAM controller in a Virtex device.

Prerequisites

Students need to have the following:
Completion of an FPGA design or participation in the two-day FPGA Tools course

Virtex Course Outline

The following topics will be discussed during the Virtex course:

Virtex series features

System level solutions solved with Virtex

Virtex architectural resources

Accessing the Virtex architectural resources during design entry

High level Virtex Applications

Essential VHDL and Synthesis for
Xilinx FPGA Technology

Location	Aug	Sept	Oct	Nov	Dec
Xilinx - San Jose, CA					16-17

This two-day course is designed to bridge the gap between having an understanding of VHDL for synthesis and specific programmable technology and learning how to write code, use specific synthesis and place & route tools to achieve the most efficient design.
The hands-on exercises take engineers through the implementation of the most common and troublesome types of design problems, such as RAM, ROM, arithmetic functions, state machines, bi-directional asynchronous IO and repeated hierarchy. The attendee will learn how to obtain the best results with a choice of synthesis tools (Exemplar, Synplicity, or Synopsys). The attendee should have previous VHDL for synthesis experience or recent attendance at a VHDL course as well as knowledge of Xilinx FPGA Technology and Implementaion Tools software.

Essential VHDL and Synthesis for Xilinx FPGA Technology Outline

The course addresses the following topics:
Day 1
Course Introduction
Xilinx Technology Overview
Definition of RTL Code (RTE)
Xilinx Design Flow Description
Language Specific Optimizations
Edge Filter Design
Lab Exercises:
- 8,000 gate Edge Filter design

Day 2
Xilinx Technology Specific Optimizations
Lab Exercises:
- Implementation of each block of the Edge Filter design

Main Topics:

- Short overview of Xilinx FPGA device architecture
- Coding styles which synthesize most easily into FPGA devices
- How to access particular FPGA features through your VHDL code (clock buffers, power-on resets or macro functions)
- Detailed look at the complete design flow
- Discussion of the common errors that occur in the design flow and how to fix them

For a more detailed description of the "Essential VHDL and Synthesis for Xilinx FPGA Technology" course, click here.

Beginning Test Bench (VHDL)

Prerequisite

The student should be familiar with the syntax and usage of VHDL (at least at the beginner course level).

Overview

This course offers a 2-day introduction to testbench design. The purpose of the course is to give VHDL designers a view of how their designs can be tested and verified using VHDL, and what resources exist within Active-VHDL to accomplish this task. The overall goal is not only to teach VHDL syntax for the various topics, but also to teach engineers to start thinking about testing during the design phase.

The points covered in the course will be applied to a real life problem such as a PCI controller, so that in the end, a complete design will have been implemented and tested. There will be a strong emphasis on hands on work in the course, with labs consisting of 50% or more of the time.

Topics include

Review of hierarchical design techniques and their application in testing

Using stimulators to test modules

Basic testbench design - the single process testbench

Testing combinatorial modules

Testing clocked Modules

Top level data type selection

Configurations and their applications to the test environment

Testing after synthesis

Testing after place and route

Using Assertions

File I/O

Different test vector techniques

Closed loop verification

Introduction to WAVES based testing

Training Locations

Domestic and International Locations

Xilinx courses are held not only in North America but also throughout Europe, Asia, India, Israel, Australia, South Africa, Singapore, and South America. The classes that are held in international locations vary in length and tuition but are based on the same material used in North America. The schedule lists the courses as well as the contact's name and phone number.

On-Site Courses

Xilinx can bring the training course to your own facility for the greatest convenience to your company. On-Site Courses Provide Additional Benefits:

No Travel Costs
On-site Xilinx training courses eliminate travel time and expenses:
- No airfare
- No hotel bills
- No car rental

Courses Tailored To Your Needs
On-site courses can be tailored to meet the specific needs of your company:
- Convenient class time and location
- Projects of a proprietary nature can be discussed openly
- Students can use their own equipment and begin an actual design during the course

Costs: North America
- Prices start at $5,000 for a minimum class size of six students.
(Prices are subject to change without notice.)

Costs: International
- Prices vary; contact your local Xilinx sales representative.
Included in course fees:
- A Xilinx-certified instructor
- Training materials for each student

Scheduling an On-site Course

To schedule a training class at your facility and determine pricing, call 877-XLX-CLASS. On-site training courses are popular, so the more advanced notice we have, the better our ability to schedule your class exactly when you want it.

Registration

Tuition

Course/Tuition Table

Course Location	Tuition	Length	Benefits
North America:
FPGA Tools	$595	2 days	- Basic implementation of Xilinx products
Foundation Interface	$195	1 day	- A complete design-entry flow
Foundation Express	$195	1 day	- Tool usage with VHDL or Verilog design examples
Getting Started with Xilinx FPGAs v2.1i	$1,000	2 days	- A jump-start for customers who are new to Xilinx FPGAs
VHDL Methodology	$795	3 days	- Introduction/Intermediate IEEE 1076
			- VHDL Targeting FPGA and simulation
Verilog Methodology	$795	3 days	- Introduction/Intermediate IEEE 1369
			- Verilog targeting FPGA and simulation
PCI Core Basics	$500	1 day	- Basics of PCI
PCI Core - Designing a PCI System	$1,000	2 days	- Develop an understanding of Xilinx PCI products
Beginning Test Bench	$1000	2 days	- Test and verify VHDL designs
2.1 Update	$250	1/2 day	- What's new in the 2.1 release of Alliance and Foundation
Virtex for XC4000 Series Users	$500	1 day	- Teaches XC4000 users Virtex
Essential VHDL and Synthesis for Xilinx FPGA Technology	$1,000	2 days	- Target VHDL for Xilinx FPGAs
On-Site Locations	Call for Quote		- Convenience
			- Focus on specific issues
International:
Multiple Locations	Varies	Varies	- Offered in over 21 countries
			- Native language
On-Site Locations	Varies	Varies	- Convenience
			- Can focus on specific issues
E-Learning Sessions	Tuition	Length	Benefits
Live	$100	1 hour	- On-line training with a knowleagable instructor allows you to ask questions and collaborate with other students from your desktop.
Recorded	$70	1 hour	- Access-focused training 24 hours a day, seven days a week, anywhere in the world.

(Prices and class schedules are subject to change without notice. Prices listed are in U.S. dollars)

Money-back Guarantee

We are so confident you will be satisfied with the benefits of a Xilinx training course that we offer the following guarantee:

- Full refund of the course cost if you are not completely satisfied.

Enrollment

Class size is limited, so early enrollment is recommended. In order to register for a class or E-Learning session, please follow the steps listed below:

1) Enroll: Contact the registrar at 877-XLX-CLASS (877-959-2527) to enroll yourself in a class or E-Learning session. You must have your tuition payment information available at the time of enrollment. We accept credit cards (Visa, Master Card, and American Express) as well as Purchase Orders and checks. Please remit payment to Xilinx, Customer Education Services, 2100 Logic Drive, San Jose, CA 95124 or fax to 408-377-7798. (We request that international customers go through a distributor if they choose to pay with a Purchase Order.)
2) Confirmation: Following enrollment, the registrar will send you a confirmation letter.
Please call (877) XLX-CLASS (877-959-2527) if you have any questions or do not receive a confirmation letter.

If you are unsatisfied or have further questions, call toll-free (877) XLX-CLASS (877-959-2527).

Student Cancellations

Course tuition is fully refundable up to two weeks before the class starts. Cancellations within two weeks (7-13 days) of the class start date will incur a 50% cancellation fee. Those who cancel fewer than 7 days prior to the class will be billed for the full amount of the tuition.

Course Cancellations

Xilinx reserves the right to cancel any class with up to 14 days notice. Typically our process is to look at a classes enrollment numbers 14 days before a class' scheduled start date and determine if the number of students enrolled is sufficient for us to hold or cancel the class. Please be aware of this when booking your travel arrangements.