Answers Database
2.1i: CE/Timing: VIRTEX CLKDLL TIMING for 2.1i
Record #2586
Product Family: Software
Product Line: FPGA Implementation
Product Part: Timing Analyzer
Product Version: 1.5i
Problem Title:
2.1i: CE/Timing: VIRTEX CLKDLL TIMING for 2.1i
Problem Description:
Urgency: Standard
General Description:
Explaines the issues associated with constraining paths of various taps of
the DLLs. In addition, how do TRCE and TA handle constraints and the
various taps of the DLL.
Solution 1:
See the external version of this solution record for a full description.
http://www.xilinx.com/support/techsup/journals/timing/solution2586/virtex_clkdll_timing.html
End of Record #2586 - Last Modified: 06/28/99 12:42 |
