Answers Database
V1.5.x COREGEN, NGDBUILD, (VIRTEX BLOCK RAM): "ERROR: BASNB Pin mismatch". COREGEN does not allow you to select the netlist bus delimiter format if one of your selections is VHDL or Verilog I nstantiation Template.
Record #4041
Product Family: Software
Product Line: Coregen
Product Part: Coregen
Product Version: c1_5
Problem Title:
V1.5.x COREGEN, NGDBUILD, (VIRTEX BLOCK RAM): "ERROR: BASNB Pin mismatch". COREGEN does
not allow you to select the netlist bus delimiter format if one of your selections is VHDL or Verilog
I
nstantiation Template.
Problem Description:
Urgency: standard
General Description:
If one of your selections under Options->Core Generator
Options is VHDL or Verilog Instantiation Template, COREGEN
v1.5.x does not allow you to select anything other than B
as the bus netlist format for the CORE Generator EDIF
Implementation Netlist..
Solution 1:
This is a known problem.
The M1.5 version of COREGEN assumes that the bus delimiter
must be "<>" in the .EDN file it generates if either
Verilog or VHDL instantiation templates are selected as
desired outputs.
The workaround requires two steps:
1. First select only the "EDIF Implementation Netlist"
option as the desired output and set the bus delimiter to
the required format, then generate the module once.
VIRTEX BLOCK RAM:
If you are generating a Virtex Block RAM, you will also need
to manually back the EDIF file that is generated in this step
to a different file name.
2. For the second iteration, *deselect* "EDIF
Implementation Netlist" FIRST to avoid overwriting the EDIF
generated the first time around, select "Verilog
(or VHDL) Behavioral Simulation Model" and/or "Instantiation
Template" for the output format, then generate the module
again.
VIRTEX BLOCK RAM:
If you are trying to generate the Virtex Block RAM, you
cannot generate HDL outputs without also selecting the EDIF
Implementation Netlist, so select both, generate the module,
then copy back the renamed EDIF file generated in step 1
to your original module name.
This problem is fixed in the COREGen v1.5.2, which is bundled
together with the A1.5isp1 and F1.5isp1 Service Packs. These
two service packs are available as of Feb. 11 and may be
downloaded from this location:
http://support.xilinx.com/support/techsup/sw_updates/index.htm
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The required EDIF bus delimiters are listed below for
some common CAE platforms:
Cadence: B
Exemplar: B(I)
Mentor: B[I]
Synplicity: B(I) if not using "syn_noarrayports" attribute, otherwise
B[I]
Synopsys: B
For further information about Synplify requirements for bus notation,
please refer to (Xilinx Solution 4272).
End of Record #4041 - Last Modified: 02/18/99 16:08 |
