Answers Database SYNPLIFY 5.x: bus notation differs across XNF, EDIF, and UCF Record #4272 Product Family: Software Product Line: Synplicity Product Part: Synplify Product Version: 5.0 Problem Title: SYNPLIFY 5.x: bus notation differs across XNF, EDIF, and UCF Problem Description: Urgency: Hot General Description: In Synplify 5.0, users must keep in mind the bus notation syntax when using EDIF, XNF, or UCF. Please see (Xilinx Solution 2649) on information on modifying the bus-notation in an EDIF generated netlist. Solution 1: In Synplify 5.x, users must keep in mind the bus notation syntax when using EDIF, XNF, or UCF. The EDIF format differs in bus notation from the XNF output file previously generated in versions 3.0 and below. +-------+-------+-------+-------------------------------------------+ | Ver. | 3.x | 5.x | Comments | +-------+-------+-------+-------------------------------------------+ | XNF | B | B | Buss signals expanded | +-------+-------+-------+-------------------------------------------+ | EDIF | X | B(I) | See Note 1; Not using "syn_noarrayports" | +-------+-------+-------+-------------------------------------------+ | EDIF | X | B[I] | See Note 1; Using "syn_noarrayports" | +-------+-------+-------+-------------------------------------------+ Note 1: Synplify 3.x doesn't produce EDIF. However, Synplify 5.x has the option of producing EDIF. Consider the EDIF snippet from Synplify 5.x: (port (array (rename tenthsout "TENTHSOUT[9:0]") 10) (direction OUTPUT)) Alliance 1.4 ------------ EDIF2NGD 1.4 doesn't handle embedded ranged strings in array names appropriately. See (Xilinx Solution 4891) for details. The signal, "TENTHSOUT[9:0]", is recognized as a 1-bit wide instead of a vector. The user can specify to have his bus ports expanded to bits with the syn_noarrayports attribute within Synplify. Please see (Xilinx Solution 504). Also, within CoreGen or Logiblox, select the bus-notation as "[]". Please read (Xilinx Solution 4041) for a description of generating CoreGen modules. Alliance 1.5i ------------ EDIF2NGD 1.5i expands an array construct, it *always* uses parenthesis. The delimiters used in the range part of the array name have no effect on the actual expansion. See (Xilinx Solution 5416) for details. Within Coregen or LogiBlox, select the bus-notation as "()". Please read (Xilinx Solution 4041) for a description of generating COREGEN modules. If you're using the syn_noarrayports attribute within Synplify, then please select the bus-notation as "[]". End of Record #4272 - Last Modified: 06/04/99 14:28

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