Answers Database V2.1i COREGEN, C_IP1: Known Issues in the C_IP1 Cores update Record #7149 Product Family: Software Product Line: LogiCore Product Part: Coregen IP Modules Problem Title: V2.1i COREGEN, C_IP1: Known Issues in the C_IP1 Cores update Problem Description: Urgency: standard General Description: Known Issues in the C_IP1 Cores update Solution 1: Foundation Flow: ------------------------- 1. (Xilinx Solution 7151): V2.1i COREGEN, C_IP1, VIRTEX, FOUNDATION: Line 3: Wrong number of fields BUS" / Foundation integration problem for Virtex BaseBLOX modules with 1-bit wide input buses Viewlogic Flow: ------------------------- 1. (Xilinx Solution 7143): V2.1i COREGEN, VIEWLOGIC: "ERROR: cleanUpSymbolFile: Could not read symbol file: <project_directory>\sym\<modulename>.1" Verilog and VHDL behavioral simulation: --------------------------------------------- 1. (Xilinx Solution 7148): V2.1i COREGEN, VIRTEX: Problems with SCLR and SINIT synchronous control signal behavioral modelling in the LD-Based LATCH module End of Record #7149 - Last Modified: 09/02/99 15:15

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