V2.1i CORE Generator User Guide Errata Page

Please review the following listing of errata in the 2.1i CORE Generator User Guide.

To access the complete database of Xilinx Solutions, please consult our Answers Search page.

Setup

VHDL Design Flow Verilog Design Flow

Setup

• Solution 6693 - V2.1i COREGEN USER GUIDE: Permissions for $XILINX/coregen/ip directory do not need to be 777

Design Flows

Verilog behavioral simulation flow

• Solution 6831 - V2.1i COREGEN USER GUIDE, VERILOG: "Error! Module name previously declared" / Verilog parent design example contains redundant module declaration
• Solution 6596 - V2.1i COREGEN, MTI, VERILOG: "WARNING[xx]: .../XilinxCoreLib/xxxx.v(xx): Redefinition of macro: true" (or TRUE, false, or FALSE) when analyzing/compiling COREGEN Verilog behavioral models

VHDL behavioral simulation flow

• Solution 6861 - V2.1i COREGEN USER GUIDE, MTI, VHDL flow: 'Error xxxmyadder8.vhd(20): near "myadder8_top" expecting COMPONENT' in VHDL testbench example