ModelSim XE 5.3 - II Simulation

Software & Version:
N/A

Audience
Xilinx users wishing to perform HDL behavioral simulation.

Prerequisites
Student should have a basic knowledge of VHDL and/or Verilog. Should have taken the module Modelsim XE - I Projects, or passed the quiz for that module. Must have an understanding of the concepts of simulation.

What is the level of the material?
Level I - Beginning

Training Duration
1 hour

Content Description
Overview of using ModelSim Xilinx Edition (XE) 5.3 to perform behavioral/RTL and timing simulation. A complete description of ModelSim's simulation windows and their debug capabilities. A complete description of running a timing simulation and the needed files. This module picks up where the module ModelSim XE - I Projects left off. The presentation includes a complete description of the simulation steps, including loading the simulator, setting breakpoints and adding signals to the waveform, source code debugging, and running the simulation.

Objectives
After completing this training, student will be able to:

• Identify each of the ModelSim debug windows
• Specify the steps to run an RTL simulation
• Identify the needed files for running timing simulation
• Specify the steps for running a timing simulation

Topics or Training Outline

• Introduction
• Debug Windows
• RTL Simulation
• Timing Simulation
• Summary

Teaching Activities
Structured Discussion X
Paper exercise(s)
Lab exercise(s)
Demo
Review questions X
Test

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