Xilinx E-Learning What is E-Learning? E-Learning Delivery Schedule Registration Information What is E-Learning? E-Learning is a new system that provides in-depth technical training sessions on Xilinx programmable logic products over the web. With E-Learning, training is organized in the form of modules. The modules are approximately one-hour sessions that focus on specific product solutions.  Using the E-Learning, we can bring the training right to your desktop. This makes technical training more convenient than ever before. E-Learning will be available as both live ($100.00 USD per module) and recorded ($70.00 USD per module) sessions. During the live E-Learning modules, participants will have the ability to ask the instructor questions, get answers and collaborate with other students, all on-line. New modules are added frequently, so bookmark this site to see the latest sessions  and schedules.  COMING SOON: Customers will be able to access recorded E-Learning modules 24 hours a day, seven days a week, anywhere in the world, and view them while listening to recorded audio that has been synchronized to each slide. In one hour, students will quickly enhance their technical capabilities. E-Learning Delivery Schedule

	9:00-10:00am PST	1:00-2:00pm PST	4:00-5:00pm PST
Feb 1	-	Floorplanner I	-
Feb 2	-	Floorplanner II	-
Feb 3	Coding Tips for Spartan Devices I (2.1)	Floorplanner III	-
Feb 4	Coding Tips for Spartan Devices II (2.1)	-	-
	9:00-10:00am PST	1:00-2:00pm PST	4:00-5:00pm PST
Feb 7	Timing Constraints in the UCF I (2.1)	-	-
Feb 8	Timing Constraints in the UCF II (2.1)	-	-
Feb 9	-	-	-
Feb 10	-	-	-
Feb 11	-	-	-
	9:00-10:00am PST	1:00-2:00pm PST	4:00-5:00pm PST
Feb 14	-	-	-
Feb 15	-	-	-
Feb 16	-	Virtex Architecture I (2.1)	-
Feb 17	-	Virtex Architecture II (2.1)	-
Feb 18	-	Virtex E Architecture (2.1)	-
	9:00-10:00am PST	1:00-2:00pm PST	4:00-5:00pm PST
Feb 21	-	-	-
Feb 22	-	-	-
Feb 23	-	Timing Constraints I (2.1)	-
Feb 24	-	Timing Constraints II (2.1)	-
Feb 25	-	Timing Constraints III (2.1)	-
	9:00-10:00am PST	1:00-2:00pm PST	4:00-5:00pm PST
Feb 28	-	-	-
Feb 29
Mar 1	Floorplanner I (2.1)	-	-
Mar 2	-	-	-
Mar 3	-	-	-
	9:00-10:00am PST	1:00-2:00pm PST	4:00-5:00pm PST
Mar 6	-	-	-
Mar 7	-	-	-
Mar 8	Floorplanner II (2.1)	-	-
Mar 9	-	Simulator (2.1)	-
Mar 10	-	Advanced Simulator (2.1)	-
	9:00-10:00am PST	1:00-2:00pm PST	4:00-5:00pm PST
Mar 13	-	-	-
Mar 14	-	-	Timing Constraints I (2.1)
Mar 15	Floorplanner III (2.1)	-	Timing Constraints II (2.1)
Mar 16	-	-	Timing Constraints III (2.1)
Mar 17	-	-	-
	9:00-10:00am PST	1:00-2:00pm PST	4:00-5:00pm PST
Mar 20	-	-	-
Mar 21	-	Intro to FPGA Design (2.1i)	-
Mar 22	-	FPGA Design II (2.1i)	-
Mar 23	-	-	-
Mar 24	-	-	-
	9:00-10:00am PST	1:00-2:00pm PST	4:00-5:00pm PST
Mar 27	-	Coding Tips for Virtex Devices I (2.1)	-
Mar 28	-	Coding tips for Virtex Devices II (2.1)	-
Mar 29	-	-	-
Mar 30	-	-	-
Mar 31	-	-	-
	9:00-10:00am PST	1:00-2:00pm PST	4:00-5:00pm PST
Apr 3	Floorplanner I (2.1)	Timing Constraints I (2.1)	-
Apr 4	-	-	-
Apr 5	-	-	-
Apr 6	-	-	-
Apr 7	Basic Virtex Architecture	-	-
	9:00-10:00am PST	1:00-2:00pm PST	4:00-5:00pm PST
Apr 10	Floorplanner II (2.1)	Timing Constraints II (2.1)
Apr 11
Apr 12
Apr 13
Apr 14
	9:00-10:00am PST	1:00-2:00pm PST	4:00-5:00pm PST
Apr 17	Floorplanner III (2.1)	Timing Constraints III (2.1)
Apr 18
Apr 19
Apr 20
Apr 21

Last Updated on 01/28/2000.
If you have any questions or comments please email Customer Education.