Thomson-CSF
Jaap Mol
CAE Consultant
Hollandse Signaalapparaten B.V. (Signaal)
subsidiary of Thomson-CSF
What are customers saying about Alliance Series software?
Jaap Mol, a CAE Consultant with Signaal, is extremely pleased with his
selection of the new Alliance Series software from Xilinx. Jaap credits
the ease-of-use, controllability, and support of industry standards of
Alliance Series software with allowing him to successfully meet his design
speed, density, price and time-to-market requirements.
About the design
Signaal utilized Alliance Series software to successfully complete an MC68360
CPU and SHARC bus interface design. The design needed to run at a clock
frequency of 25 MHz. Jaap chose to use the Xilinx Alliance Series to implement
an XC4010E-4PQ208 FPGA. Not only did the design run at the required frequency,
but it used only 70% of the CLBs and 80% of the IOBs. In addition, all
I/O pins were locked to enable concurrent design of the PCB layout.
The design flow was easy-to-use!
The design was entered using VHDL, verified using a leading VHDL simulator,
and synthesized/optimized with a leading synthesis tool. The same VHDL
test bench was used to simulate the behavioral RTL design and the implemented
design, before and after place and route. (See figure 1.0). The synthesis
tool generated an industry standard EDIF netlist, containing both gate
and connectivity information, which was then directly implemented by the
Xilinx next generation software technology.
Powerful incremental design capabilities
According to Jaap, “The enhanced capabilities in the Design Manager allows
for true incremental design capabilities. If changes have been made
to the logic design (e.g., the netlist), it is referred to as a new version
of the design. If the design is mapped into another device, package, or
speed-grade, this can be referred to as a new revision. This allowed
us to make tradeoffs, without loss of previous results.”
Seamless support of industry standard netlist
Jaap was pleased with Xilinx’s support of industry standards, which makes
the interface to third party EDA vendors seamless. “Place & route
tools also generate a standard VHDL (Verilog) netlist and SDF file with
the timing information, making it possible for us to perform simulation
both before and after place & route. Improvements include: usability
of the software; controllability of the tools; new help and report browsing;
and interface format to existing EDA tools. Availability of the VITAL compliant
VHDL library makes it possible to use one test bench, one simulator, and
one language on any level of abstraction. We believe this was the reason
why interfaces from the synthesizer and simulator did not cause any major
problems.”
Powerful auto-interactive M1 implementation tools
Advanced place & route tools deliver enhanced productivity through
a combination of powerful incremental design capabilities and optimization
technology. Alliance Series software delivers a combination of attributes
that ensure higher device utilization and design performance through push-button
flows:
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New structured placement algorithms which automatically optimize the alignment
of busses using tri-state buffers
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Enhancements to the circuit packaging algorithms
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Improvements in timing driven place-and-route capabilities that increase
performance by 15%
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In summing up his experience with Alliance Series software, Japp
concluded by saying, “Xilinx has obviously put a lot of effort into the
development of this new release. The new tools helped cut down our design
time significantly, which translated into reduced time-to market.” |
Program
Overview