Alliance Series v2.1i Software The Industry's most advanced Programmable Logic Design Tools, integrated into your design environment

More Information: Enabling your 2.1i software for Virtex-E Supporting 2 Million Gate FPGA Design The Value of Alliance EDA Partnerships Alliance EDA partners Alliance Series Product Configurations Alliance Series Feature Highlights Feature Summary Platform and System Requirements ModelSim Xilinx Edition

Buy Xilinx Products On-line! The following Alliance Series configuration can be purchased on-line at the Xilinx Silicon Xpresso Cafe:   Alliance Series Base Alliance Series Standard ModelSim Xilinx Edition

Version 2.1i of the Alliance Series software has been optimized to deliver efficient, high density design flows for Xilinx 2 Million gate programmable logic devices.  Dramatic improvements in the implementation algorithms for high density FPGAs and the support of a variety of system level design features, enable Alliance Series designers to create high-performance designs using the ultra high density extensions to the Virtex family.  Additionally, fast compile times and the embedded Xilinx Core Generator System help make targeting a design on a multi-million gate device a reality.

• Compile 100,000 System Gates in less than a minute

	The Version 2.1i design solutions continue Xilinx' trend of cutting place and route runtime in half, while maintaining or improving design performance.  The accumulation of runtime improvements now enable the compilation of the 100,000 system gate Virtex devices in less than one minute.
And, given the broad suite of cores supporting Virtex FPGAs today, high level systems functions including the 64 bit/66 MHz PCI interface can be implemented in less than 20 minutes.  Fast compile times translate to more turns per day and greater productivity.

• Embedded CORE Generator tool

The Xilinx CORE Generator, now embedded in the Alliance Series v2.1i software, simplifies the integration of intellectual property into your design by providing drop-in access to flexible, high performance FPGA-based cores.
The CORE Generator tool includes an intuitive navigation tree for searching and selecting cores from Xilinx or Xilinx AllianceCORE Partners.  Additionally, Xilinx LogiCORE modules utilize Smart-IP technology which ensures that Xilinx Cores use the architectural advantages of Xilinx FPGAs resulting in high performance, predictable, repeatable, and flexible core-based designs.

In order to ensure that designers can take advantage of the many advances in EDA technology, Xilinx has built close relationships with many of the industry's leading EDA tool vendors, resulting in timely support of emerging design methodologies.  Combining the strengths of our partner's tools with our own advanced implementation technology provides you with a powerful overall design solution, the highest clock performance and the highest densities in the industry. To learn more about the Alliance EDA program and our Alliance EDA partners, visit our Alliance EDA pages.

Alliance Series software supports a variety of devices and is the first to support the industry's first two million gate FPGA.  Alliance Series software is available in a Base, Standard or, in September, 1999, Elite configurations.  Each configuration is available for use on either a PC or workstation platform and are licensed in accordance with the Annual License Program.  The primary difference between Alliance Series product configurations is the size of XC4000E/X and Virtex devices which can be implemented. The chart below shows the specific device support for each configuration.
 

Device Support
Alliance Base (v2.1i Now Shipping) CPLDs XC9500/XL/XV	Alliance Standard (v2.1i Now Shipping!) CPLDs XC9500/XL/XV	Alliance Elite (Available September 1999!) CPLDs XC9500/XL/XV
FPGAs Virtex XCV50 XC4000E/X  (Up to XC4010E/X)* All Spartan/XL All XC3x00A/L XC5200 (Up to XC5210)	FPGAs Virtex (Up to XCV1000E) All XC4000E/X All Spartan/XL All XC5200 All XC3x00A/L	FPGAs All Virtex/E All XC4000E/X All Spartan/XL All XC5200 All XC3x00A/L

*Note:The XC4013L and XC4013XL devices are supported in the Alliance Series Base System.

The Alliance Series Elite configuration will also offer the Xilinx Internet Team Design development option when it becomes available in November of 1999.

Graphical Constraints Editor Achieve your desired design performance on the first pass. You are guided to an optimum constraint setting through a display of clocks and ports in the design, in an easy-to-use format. No need to know the names of nets and components. Stamp Model Generation LMG Smartmodel Generation Supports the use of board level Static Timing Analysis tools: Mentor Graphics' Tau Viewlogic's Blast Accelerate board level design verification Supports the use of board level Simulation Tools Efficient modeling language accurately defines FPGA I/O behavior Dramatically accelerates system level verification In-System Debugging with Probe Provides real time access to any internal signal for system level debugging Does not require modifications to source design. Does not require design recompilation. How to use Probe Minimum Timing Delays Voltage and Temperature Pro-rating Guarantee your design performance with both minimum and maximum process delay numbers. Test how fast your design can perform under favorable operating conditions. HDL Synthesis HDL Verification Benefit from premier partnerships with the industry's leading synthesis vendors, providing you the highest performance for FPGAs and CPLDs. Reduce your design time by 25% by adopting an HDL testbench methodology. Two design guides explain Xilinx' leading technology and how it works with our HDL simulation partners. Floorplanner Increase your design's performance by as much as 40%. Designers can choose to add their knowledge of the structure of the design methodology by employing a floorplanner.

The Alliance Series supports the full line of Xilinx FPGAs and CPLDs including our XC3000, XC4000E/X/XL/XV, XC5200, XC9500, Spartan/XL and Virtex families. Also included are the industry's most advanced implementation technology. The table below lists the Alliance Series features included in each of the three product configurations.
 

Features		Alliance Series Part Numbers
		ALI-BAS		ALI-STD		ALI-ELI
EDA Libraries and Interfaces for Cadence, Exemplar, Mentor, MTI, Synopsys, Synplicity and Viewlogic
Internet Enabled Design Features
Support for Internet Team Design (Xilinx iTD)
Xilinx CORE Generator System
LogiBLOX Module Generator
Turns Engine (Workstation Only)
Simulator (Functional and Timing)
HDL Simulation Libraries  (UniSim and Simprim)
EDIF, VHDL (VITAL), and Verilog  Back Annotation
Stamp Models
Logic Modeling SmartModels
Implementation Tools Design Manager, Flow Engine, Timing Analyzer, Hardware Debugger, JTAG Programmer, PROM File Formatter, Graphical Constraint Editor, Graphical Floorplanner
CPLD Devices Supported XC9500 & XC9500XL (All)
FPGA (Base System Device Support) XC3x00A/L (All)  XC4000E/X (Up to XC4010E/X)* XC5200 (Up to XC5210) Spartan and SpartanXL Devices (All) Virtex XCV50
FPGA (Standard System Device Support) XC3x00A/L (All)  XC4000E/X/XL/XLA/XV (All) XC5200 (All) Spartan and SpartanXL Devices (All) Virtex/E (Up to XCV1000 & XCV1000E)
FPGA (Elite System Device Support) XC3x00A/L (All)  XC4000E/X/XL/XLA/XV (All) XC5200 (All) Spartan and SpartanXL Devices (All) Virtex and Virtex-E (All)

For more information on the Xilinx Software Solutions, please visit the Software Solutions Page or contact your local Xilinx sales office.

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