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Alliance
Series v2.1i Software
The Industry's most
advanced Programmable Logic Design Tools, integrated into your design environment
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The Alliance Series software is
designed for companies who have made an investment in an EDA environment
customized to suit the needs of their design engineers. The Xilinx
Alliance Series plug and plays by leveraging open systems standards, interfaces
and formats such as EDIF, SDF, VHDL, VITAL/Verilog and STAMP. Combining
the strengths of our EDA partner tools with the advanced implementation
features found in the Xilinx Alliance Series Software provides digital
designers the ultimate in flexibility and design performance.
Supporting
up to 2 Million Gate FPGA Design
Version 2.1i of the Alliance Series software has been optimized to deliver
efficient, high density design flows for Xilinx 2 Million gate programmable
logic devices. Dramatic improvements in the implementation algorithms
for high density FPGAs and the support of a variety of system level design
features, enable Alliance Series designers to create high-performance designs
using the ultra high density extensions to the Virtex family. Additionally,
fast compile times and the embedded Xilinx Core Generator System help make
targeting a design on a multi-million gate device a reality.
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Compile 100,000 System Gates in less than a minute
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The Version 2.1i design solutions continue Xilinx' trend of cutting
place and route runtime in half, while maintaining or improving design
performance. The accumulation of runtime improvements now enable
the compilation of the 100,000 system gate Virtex devices in less than
one minute. |
And, given the broad suite of cores supporting Virtex FPGAs
today, high level systems functions including the 64 bit/66 MHz PCI interface
can be implemented in less than 20 minutes. Fast compile times translate
to more turns per day and greater productivity. |
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Embedded CORE Generator tool
The Xilinx CORE Generator, now embedded in the Alliance
Series v2.1i software, simplifies the integration of intellectual property
into your design by providing drop-in access to flexible, high performance
FPGA-based cores. |
The CORE Generator tool includes an intuitive navigation
tree for searching and selecting cores from Xilinx or Xilinx AllianceCORE
Partners. Additionally, Xilinx LogiCORE modules utilize Smart-IP
technology which ensures that Xilinx Cores use the architectural advantages
of Xilinx FPGAs resulting in high performance, predictable, repeatable,
and flexible core-based designs. |
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The
Value of Alliance EDA Partnerships
In order to ensure that designers can take advantage of the many advances
in EDA technology, Xilinx has built close relationships with many of the
industry's leading EDA tool vendors, resulting in timely support of emerging
design methodologies. Combining the strengths of our partner's tools
with our own advanced implementation technology provides you with a powerful
overall design solution, the highest clock performance and the highest
densities in the industry. To learn more about the Alliance EDA program
and our Alliance EDA partners,
visit our Alliance EDA pages.
Alliance
Series Product Configurations
Alliance Series software supports a variety of devices and is the first
to support the industry's first two million gate FPGA. Alliance Series
software is available in a Base, Standard or, in September, 1999, Elite
configurations. Each configuration is available for use on either
a PC or workstation platform and are licensed in accordance with the Annual
License Program. The primary difference between Alliance Series
product configurations is the size of XC4000E/X and Virtex devices which
can be implemented. The chart below shows the specific device support for
each configuration.
Device Support
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Alliance Base
(v2.1i Now Shipping)
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CPLDs |
XC9500/XL/XV |
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Alliance Standard
(v2.1i Now Shipping!)
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CPLDs |
XC9500/XL/XV |
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Alliance Elite (Available September 1999!)
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CPLDs |
XC9500/XL/XV |
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FPGAs |
Virtex XCV50 |
XC4000E/X
(Up to XC4010E/X)* |
All Spartan/XL |
All XC3x00A/L |
XC5200
(Up to XC5210) |
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FPGAs |
Virtex
(Up to XCV1000E) |
All XC4000E/X |
All Spartan/XL |
All XC5200 |
All XC3x00A/L |
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FPGAs |
All Virtex/E |
All XC4000E/X |
All Spartan/XL |
All XC5200 |
All XC3x00A/L |
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*Note:The XC4013L and XC4013XL devices are supported
in the Alliance Series Base System.
The Alliance Series Elite configuration will also offer the Xilinx Internet
Team Design development option when it becomes available in November of
1999.
Alliance
Series Feature Highlights
Graphical Constraints Editor
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Achieve your desired design performance on the first pass.
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You are guided to an optimum constraint setting through a display of clocks
and ports in the design, in an easy-to-use format.
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No need to know the names of nets and components.
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Stamp Model Generation |
LMG Smartmodel Generation |
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Supports the use of board level Static Timing Analysis tools:
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Mentor Graphics' Tau
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Viewlogic's Blast
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Accelerate board level design verification
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Supports the use of board level Simulation Tools
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Efficient modeling language accurately defines FPGA I/O behavior
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Dramatically accelerates system level verification
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In-System Debugging with Probe
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Provides real time access to any internal signal for system level debugging
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Does not require modifications to source design.
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Does not require design recompilation.
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How to use Probe
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Minimum Timing Delays |
Voltage and Temperature Pro-rating |
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Guarantee your design performance with both minimum and maximum process
delay numbers.
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Test how fast your design can perform under favorable operating conditions.
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HDL Synthesis |
HDL Verification |
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Benefit from premier partnerships with the industry's leading synthesis
vendors, providing you the highest performance for FPGAs and CPLDs.
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Reduce your design time by 25% by adopting an HDL testbench methodology.
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Two design guides explain Xilinx' leading technology and how it works with
our HDL simulation partners.
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Floorplanner
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Increase your design's performance by as much as 40%.
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Designers can choose to add their knowledge of the structure of the design
methodology by employing a floorplanner.
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Feature
Summary
The Alliance Series supports the full line of
Xilinx FPGAs and CPLDs including our XC3000, XC4000E/X/XL/XV, XC5200, XC9500,
Spartan/XL and Virtex families. Also included are the industry's most advanced
implementation technology. The table below lists the Alliance Series features
included in each of the three product configurations.
Features |
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Alliance
Series Part Numbers |
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ALI-BAS
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ALI-STD
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ALI-ELI
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EDA Libraries and Interfaces for Cadence, Exemplar,
Mentor, MTI, Synopsys, Synplicity and Viewlogic |
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Internet Enabled Design Features |
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Support for Internet Team Design (Xilinx iTD) |
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Xilinx CORE Generator System |
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LogiBLOX Module Generator |
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Turns Engine (Workstation Only) |
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Simulator (Functional and Timing) |
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HDL Simulation Libraries
(UniSim and Simprim) |
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EDIF, VHDL (VITAL), and Verilog
Back Annotation |
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Stamp Models |
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Logic Modeling SmartModels |
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Implementation Tools
Design Manager, Flow Engine, Timing Analyzer, Hardware
Debugger, JTAG Programmer, PROM File Formatter, Graphical Constraint Editor,
Graphical Floorplanner |
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CPLD Devices Supported
XC9500 & XC9500XL (All) |
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FPGA (Base System Device Support)
XC3x00A/L (All)
XC4000E/X (Up to XC4010E/X)*
XC5200 (Up to XC5210)
Spartan and SpartanXL Devices (All)
Virtex XCV50 |
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FPGA (Standard System Device Support)
XC3x00A/L (All)
XC4000E/X/XL/XLA/XV (All)
XC5200 (All)
Spartan and SpartanXL Devices (All)
Virtex/E (Up to XCV1000 & XCV1000E) |
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FPGA (Elite System Device Support)
XC3x00A/L (All)
XC4000E/X/XL/XLA/XV (All)
XC5200 (All)
Spartan and SpartanXL Devices (All)
Virtex and Virtex-E (All) |
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*Note:The XC4013L and XC4013XL devices are supported
in the Alliance Series Base System
Platform
Support and System Requirements
Platform Support
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IBM PC or Compatible
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Workstation
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Win95/Win98
(Chinese, Korean, US, Japanese)
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Windows NT 4.0
(US, Japanese)
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NEC98
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Solaris 2.6 & 2.7
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HP-UX 10.2
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The memory requirements for both RAM and
hard disk space will vary depending on your target device family and size
as well as the unique characteristics of your design. For detailed
listings of the memory requirements specific to your installation, please
reference the Alliance
Series 2.1i Release Notes and Installation Guide on WebLINX. |
For more information on the Xilinx Software Solutions, please visit
the Software Solutions Page or contact
your local Xilinx sales office.
More
Information
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