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To improve runtime for timing driven implementation, the place and route
defaults have changed to NOT run Cost Based and Delay Based Clean-up passes.
Because of this change, you may notice lower design performance results
from PAR. This will occur on designs that are run in v2.1i with no timing
constraints applied (non-timing driven). To get a more "realistic" estimate
of how your design will perform without any timing constraints applied,
please follow this recommendation:
- Implement your design until PAR has completed.
- Open up the Flow Engine on your (Routed,OK) revision.
- Under Setup-> FPGA Re-entrant Route, specify the number of clean-up
passes to be run.
- Click OK.
- In the Flow Engine, select Flow->Step Back.
- Select Flow->Run.
- Check the Reports Browser (P&R Report/Post Layout Timing Report) for
improved performance results.
See Answers Database.
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