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How can place and route results be improved without adding timing constraints?

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To improve runtime for timing driven implementation, the place and route defaults have changed to NOT run Cost Based and Delay Based Clean-up passes. Because of this change, you may notice lower design performance results from PAR. This will occur on designs that are run in v2.1i with no timing constraints applied (non-timing driven). To get a more "realistic" estimate of how your design will perform without any timing constraints applied, please follow this recommendation:

  1. Implement your design until PAR has completed.
  2. Open up the Flow Engine on your (Routed,OK) revision.
  3. Under Setup-> FPGA Re-entrant Route, specify the number of clean-up passes to be run.
  4. Click OK.
  5. In the Flow Engine, select Flow->Step Back.
  6. Select Flow->Run.
  7. Check the Reports Browser (P&R Report/Post Layout Timing Report) for improved performance results.

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