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Xilinx Reed-Solomon Solution


Brings flexibility, time-to-market and cost advantages to high-volume wireless, mass storage and multi-media markets.

  • Parameterizable Reed-Solomon cores for Virtex/-E and Spartan-II

  • Reed-Solomon in Spartan-II below ASSP prices (Xilinx at Work)
 

 

Reed-Solomon Lounges (Customers only)


Overview

 
Xilinx provides user-parameterizable LogiCORE Reed-Solomon encoder and decoder cores for customers designing digital communication, mass storage, and multimedia systems. By using Xilinx Reed-Solomon solution users can significantly reduce implementation cost and accelerate time-to-market compared to fixed function ASSP alternatives. The cores support Xilinx Virtex/-E, Spartan-II, Spartan/-XL and XC4000 FPGA families. Implemented in Spartan-II, the Reed-Solomon solution costs less than $10 in high-volume making it ideal for many emerging high-volume markets.

Click here for FAQ, data sheets, configuration demo, and other links.

More information on
Reed-Solomon with

Spartan-II Logo

on Xilinx at Work

The Basics of Reed-Solomon

Reed-Solomon is a type of Forward Error Correction (FEC) commonly used in data transmission and storage applications, such as wireless communication units, DSL modems, Digital TV, RAID, DVB and DVD products. By adding redundancy before data transmission and storage, a Reed-Solomon codec (encoder/decoder) can detect and correct errors for blocks of data. There are many different standards that are used in different applications, for example DVB, ATSC, and IESS-308.

Core Features

 
  • High-speed compact Reed-Solomon Decoder and Encoder
  • Automatically configured from user parameters (demo Decoder/Encoder)
  • Supports all major coding standards and custom implementations
  • Available for Virtex/-E, Spartan-II, Spartan/-XL, XC4000
  • Downloadable over the Internet gives instant access to latest releases
  • Incorporates Xilinx Smart-IP Technology for design predictability

Jointly developed with

Logo ISS

a Xilinx AllianceCORE partner

Xilinx Smart-IP Technology

The definition for Xilinx Smart-IP technology is a combination of:

  • Xilinx FPGA architecture with segmented routing and distributed as well as block memory, which makes it well tailored to core implementation
  • Xilinx software and core features allowing predetermined placement and routing

The result is predictable design implementation where performance and functionality are consistent independently of core placement, number of cores used, surrounding user logic, device size, and used EDA tools. Xilinx Smart-IP Technology is vital for successful system-on-a-chip designs.

Smart-IP Illustration

Implementation Example

Features

Typical Reed-Solomon
ASSP

The Xilinx Reed-Solomon in Spartan-II

Polynomial

Fixed

Parameterizable

Symbol Width

Fixed

Parameterizable

Block Length

Programmable (3 - 255)

Parameterizable (3 - 4095)

Correctable Errors

Programmable (1 - 10)

Parameterizable (1 - 64)

Erasure Handling

Fixed

Parameterizable

Maximum Throughput

12.5 Mbytes/sec

Decoder: 62 Mbytes/sec*
Encoder: 108 Mbytes/sec*

Latency

1181 cycles

418 cycles*

Cost

$20

$9.95 *º

* With core configuration comparable to listed ASSP example.
º Cost based on 250K resale price for XC2S100

Ordering information

Part number Product Description Supported Devices
DO-DI-RSE Reed-Solomon Encoder Virtex-E, Virtex, Spartan-II, Spartan/-XL, XC4000
DO-DI-RSD Reed-Solomon Decoder

Please contact your local Xilinx Sales Office for pricing information or to place an order. Xilinx LogiCORE Reed-Solomon Products are provided under Xilinx standard pdf LogiCORE Reed-Solomon license agreement.

Additional Information

Get Acrobat to view the pdf PDF files on this page.

Additional Spartan-II Information

* Note that a browser that supports the JDK1.1.5 version of Java, such as Netscape Communicator 4.5 or later, is required to view the core generation GUI's. Netscape Communicator 4.5 or later may be downloaded from hereInternet Link. Java must be enabled in the browser preferences.