The Configuration Problem Solver

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Has either LDC gone high or HDC gone low?

Yes, either the LDC has gone high, or the HDC has gone low, or both. No, the LDC is low and the HDC is high.

The purpose of this question is to determine if the I/Os have been released. Given that the DONE pin has gone high the FPGA should be in the STARTUP sequence. During the startup sequence when the IOs are released the LDC and HDC become user programmable IOs. During configuration LDC and HDC are LOW and HIGH, respectively. If they are not used in the design then the LDC should tristate and pull high. If they are used in the design then they should be responding according to the functionality of the design that the FPGA has been configured for once released. Check the Programmable Logic Data Book for the pin locations for LDC and HDC.