What Needs Constraining?
Internal clock speed for one or more clocks
I/O speed
Logic using multi-cycle clocks
Pin to Pin timing
Pin Locations & Logic Locations
OUT1
OUT2
2 Levels of Logic
Clk & CE Speed
I/O Speed
I/O Speed
Pin Locations
Pin Locations
Logic Locations
1 Level of Logic
Q
D
Q
D
CLK
Previous slide
Next slide
Back to first slide
View graphic version