The OFFSET IN - ‘BEFORE’ constraint

NET Din OFFSET = IN 20nS BEFORE CLK

CLK

UPSTREAM DEVICE

FPGA

This says, Data will be valid here, 20nS BEFORE the clock arrives here.

In other words: “The Data to be registered in the FPGA will be available on the FPGA’s input Pad 20ns BEFORE

the clock pulse is seen by the FPGA’s clock pad.”

Therefore, the M1 tools will calculate: Maximum_Allowable_Internal_P2S_Delay = OFFSET + internal_CLK_delay.

The tools can automatically

calculate and control internal

data and clock delays to meet

TsuFF

Tbufg

20ns

Data Out

of DEV1 on

this edge.

Data registered

in FPGA on

this edge.

Internal

delay

Din

CLK

Valid

Designer must ensure that

T(clock_period) - 20ns = ext-delay