The OFFSET IN - ‘AFTER’ constraint

NET CLK PERIOD = 45nS;

NET Din OFFSET = IN 16nS AFTER CLK;

CLK

UPSTREAM DEVICE

FPGA

This says, Data will be valid here, 16nS AFTER the clock arrives here!…..

In other words: “The Data to be registered in the FPGA will be available on the FPGA’s input Pad 16ns AFTER the clock

pulse is seen by the Upstream Device.” For the purposes of the OFFSET constraint syntax, assume no skew on CLK

between the chips. A PERIOD constraint is required to indicate when the subsequent clock pulse will be seen by the FPGA

to clock in the Data (Maximum_Allowable_Internal_P2S_Delay = PERIOD - OFFSET + internal_CLK_delay).

16ns

Data Out

of DEV1 on

this edge.

Data registered

in FPGA on

this edge.

Din

CLK

For this example, the max. P2S delay

would be calculated by M1 as :

45ns-16ns+3ns = 32ns.

(Assuming internal CLK delay is 3ns.)

Valid