The OFFSET OUT - ‘BEFORE’ constraint

NET CLK PERIOD = 45nS;

NET Din OFFSET = OUT 25nS BEFORE CLK;

This says, Data will be valid here, 25nS BEFORE the clock arrives here!…..

In other words: “The Data to be registered in the Downstream Device will be available on the FPGA’s output Pad 25ns BEFORE

the clock pulse is seen by the Downstream Device.” For the purposes of the OFFSET constraint syntax, assume no skew on

CLK between the chips. A PERIOD constraint is required to indicate when the initial clock pulse was seen by the FPGA

to clock out the Data (Maximum_Allowable_Internal_C2P_Delay = PERIOD - OFFSET - internal_CLK_delay).

25ns

Data Out

of FPGA on

this edge.

Data Into

DEV2 on

this edge.

DEV2

FPGA

For this example, the max. C2P delay

would be calculated by M1 as :

45ns-25ns-3ns = 17ns.

(Assuming internal CLK delay is 3ns.)