The OFFSET OUT - ‘AFTER’ constraint

NET Din OFFSET = OUT 22nS AFTER CLK

This says, Data will be valid here, 22nS AFTER the clock arrives here!…..

In other words: “The Data to be registered in the Downstream Device will be available on the FPGA’s output Pad 22ns AFTER

the clock pulse is seen by the FPGA.” (Maximum_Allowable_Internal_Dout_Delay = OFFSET - internal_CLK_delay).

22ns

Data Out

of FPGA on

this edge.

Data clocked

into DEV2 on

this edge.

DOWNSTREAM DEVICE

FPGA

Designer must ensure that

T(clock_period) - 22ns = ext-delay

ext-delay = sufficient time for

external delays involved with

meeting DEV2 setup time.

Valid