Slide 9 of 22 Notes:  

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To simplify the DSP design process software tools are now available that create standard DSP building blocks in the form of parameterizable FPGA cores. Functions such as filters, storage elements, and arithmetic operations have parameterizable bit widths. System level DSP modeling tools can be used to determine optimal bit widths for each stage of the data path processing thereby minimizing the number of programmable resources required for implementation.

FPGA core generator software builds the core with your parameters producing custom building blocks that can be integrated with other cores and with logic defined by standard HDL synthesis software.

The quality of results using logic synthesis has dramatically improved with new FPGAs. Larger device sizes mean the you can afford to trade off hardware resources for design expediency.

The combination of parameterizable DSP cores and VHDL / Verilog design methodology is proving itself to be the ideal DSP design approach for FPGAs.