The Configuration Problem Solver

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CONCLUSION

A DataFrame Error has been detected.

During configuration the FPGA checks each DataFrame for the appropriate start and stop bits and by default performs a Cyclic Redundancy Check (CRC) to ensure the tramsitted data was received correctly. If any of these bits cause a mismatch then the configuration process is aborted and the INIT is driven low to signal the error. When configuring in Express Mode the CRC check MUST BE DISABLED. If the CRC is not disabled in Express Mode then a frame error will occur.

With the CRC disabled, each frame is still checked for start and stop bits (Constant Field Check). If there is a mismatch on the stop bits then a frame error will still occur causing the INIT to drive Low. The following are some possibilities why this may have occured.

(1) Bitstream targeted for wrong device.

(2) Timing violations and clock glitches.

(3) Data loaded backwards.

(4) Memory algorithm is outdated.

(5) The Mode Pins are set incorrectly.

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