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The Configuration Problem Solver
CONCLUSION
A DataFrame Error has been detected.
During configuration the FPGA checks each DataFrame for the appropriate start and stop bits and by default performs a Cyclic Redundancy Check (CRC) to ensure the tramsitted data was received correctly. If any of these bits cause a mismatch then the configuration process is aborted and the INIT is driven low to signal the error. The following are some possibilities why this may have occured. (1) Bitstream targeted for wrong device. (2) Timing violations and clock glitches. (4) Memory algorithm is outdated. See also related answers. |
| HISTORY |
| Family: SpartanXL |
| Mode: Master Serial |
| DONE: LOW |
| INIT: LOW |