The Configuration Problem Solver
Has either LDC gone high or HDC gone low?
The D/P pin is released as part of the Startup Sequence. The Startup Sequence has a programmable order controlled by software options during bitstream generation. By default the D/P is released first in the Startup Sequence; however, your implementation may have specified to release the D/P last. If this is the case and the I/Os have been released, noted by LDC or HDC, then the FPGA has entered the Startup Sequence. |
HISTORY |
Family: XC3000 |
Mode: Slave Serial |
D/P: LOW |
INIT: HIGH |