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The Configuration Problem Solver
CONCLUSION
The STARTUP Sequence has not completed.
To complete the STARTUP Sequence all that is needed are a few more clock cycles. Another possibility is that the D/P pin is being held low externally, or is not being pulled up. The D/P pin is an Open-Drain driver that must be pulled up to achieve a logic high. While the FPGA does have a programmable internal pullup resistor to the D/P pad, we recommend using an external 4.7Kohm resistor. If necessary, seperate the D/P pin from the board to verify if an external source is holding it low. See also the related answers. Related Answers |
| HISTORY |
| Family: XC3000 |
| Mode: Slave Serial |
| D/P: LOW |
| INIT: HIGH |
| LDC: HIGH |