New FPGAs DSP Features

Logic Cell:

Look-up table or

Distributed RAM

Programmable Interconnect

Block RAM

Block RAM

Block RAM

• Distributed RAM - FIR Filter

• Block RAM - FFT buffers

• Shift registers - D.A. & serial

• Multiply “AND” - 200 MHz

• DLL - Multi-rate clocks

FPGAs are scalable, monolithic arrays of programmable logic building blocks - logic cells - combined with programmable interconnect resources.

The four input look-up table architecture of logic cell is particularly useful for DSP algorithms. It can be used for either arithmetic or distributed memory , the two basic DSP requirements.

4th generation FPGAs also incorporate many DSP friendly features:

Distributed RAM for FIR filter data buffers
Block RAM for FFT buffers

Shift registers for distributed arithmetic and serial arithmetic
Multiply “AND” gate for efficient high speed parallel multipliers
DLL for generating multi-rate clocks for decimating and interpolating filters