The Configuration Problem Solver

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Timing violations and signal glitches.

Typically when connecting an FPGA directly to a memory element performance characteristics and timing specifications are not a point of concern. However, if the address or data paths are being passed through secondary devices or are subject to any extra delay, then the access time of the storage element becomes important relative to the required setup time for the FPGA. Verify that the timing characteristics for the configuration data path of the application conforms to the Configuration Switching Characteristics and Timing Specifications outlined in the Xilinx Programmable Logic Data Book.

Signal glitching may be caused by interference from other signals traced close by or by "Ground Bounce" from other devices. Make sure that the FPGA is well decoupled. Xilinx recommends a 0.1uF and 0.01uF capacitor pair per VCC/GND pair. Try to place these as close to the FPGA as possible. More than an inch distance would make them useless.