The Configuration Problem Solver

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The Mode Pins are set incorrectly.

To configure in the Master Parallel Mode the Mode Pins <M2:M1:M0> must be set to <100> for Parallel Up Mode, and <110> for Parallel Down Mode. In the Parallel Up Mode the Address lines start at <00000h> and count up. In the Parallel Down Mode the Address lines start at <1FFFFh> and count down. The Mode pins use the TTL standard threshold values (VILmax=0.8 Volts and VIHmin=2.4 Volts). Make sure that these pins show good strong logic values. Measure these pins at the actual FPGA package to insure there aren't any connection errors on the board. If any of these pins were left unconnected add external pullup or pulldown resistors as needed. Xilinx FPGAs have internal pullup resistors at the Mode pin pads. The strength of these pullups are not tested and some may be stronger than others. A pulldown strength of 1Kohm and pullup strength of 4.7Kohm is recommended.