The Configuration Problem Solver

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CONCLUSION

The STARTUP Sequence has not completed.

To complete the STARTUP Sequence all that is needed are a few more clock cycles. The clock signal that is used for the STARTUP state machine is the CCLK by default. However, another (USER) clock may be specified by using the STARTUP component in the design and selecting the startup clock options for bitstream generation. Be sure which has been selected for your design implementation and assert the clock. If CCLK is specified as the Startup clock then more CCLKs may be generated by strobing in more bytes of dummy data.

Another possibility is that the DONE pin is being held low externally, or is not being pulled up. The DONE pin is an Open-Drain driver that must be pulled up to achieve a logic high. While the FPGA does have a programmable internal pullup resistor to the DONE pad, we recommend using an external 4.7Kohm resistor. If necessary, seperate the DONE pin from the board to verify if an external source is holding it low.

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