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The Configuration Problem Solver
CONCLUSION
The Configuration Memory is not Full.
In order for the FPGA to enter the Startup Sequence and complete the configuration process all Data Frames must be correctly loaded into memory resulting in the memory being Full. DOUT goes High to indicate when this has occurred. A possibility may be that the configuration process was not allowed to complete or was terminated too early, or perhaps no configuration data was even sent. Check the number of configuration data bytes that have been loaded. The following are several typical reasons why an FPGA would ignore attempts to configure it. (1) The Mode Pins are set incorrectly. (2) The Data Pins D<7:0> are not connected to the board correctly. (3) The CCLK is not transitioning or is not correctly connected. (4) Boundary Scan has been invoked. See also related answers. |
| HISTORY |
| Family: SpartanXL |
| Mode: Express |
| DONE: LOW |
| INIT: HIGH |
| DOUT: LOW |
| CS1: HIGH |