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The ADPCM32 speech codec core is an optimized, low cost, ITU compliant solution to accelerate product time-to-market
for communications applications.
- 32-Channel ADPCM Core for Virtex, Virtex-E and Spartan-II
- ADPCM Solution available now for prices below ASSPs
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ADPCM Lounge (Customers only)
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Overview
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Xilinx provides a fixed netlist LogiCORE solution for the 32-channel ADPCM codec core for communications applications.
By using a Xilinx ADPCM solution, users can significantly reduce implementation cost and accelerate time-to-market
compared to fixed function Application Specific Standard Product (ASSP) alternatives. The core is available immediately
and supports Xilinx Virtex, Virtex-E and Spartan-II FPGA families. This new core creates an ideal solution for
many emerging communications markets such as WLL's, DECT/WDCT cordless and Internet phone systems, satellite communications,
central office DSLAMs, computer telephony and next generation PBXs.
Click here for FAQ, data sheet, overview presentation, and other links. |
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The Basics of ADPCM
ADPCM, adaptive differential pulse code modulation, is a popular ITU defined protocol used in communications.
ADPCM encoded voice traffic provides excellent voice quality commonly used as an interchange between packet voice,
PSTN, and PBX networks. This protocol is responsible for performing compression and expansion of speech wave forms
for transmission, storage and reconstruction. The ADPCM encoder/decoder receives PCM input bit flow at 64 kbit/s
(8 kHz sampling x 8-bit PCM word) and processes in real-time to produce a 40, 32, 24 or 16 kbit/s (8 kHz x 5,4,3
or 2-bit ADPCM word).
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Core Features
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- Fully compliant with ITU G.726, G.721 and G.723
- 32 duplex channels or up to 64 independent single mode channels
- Accepts A-, µ -law and uniform PCM data and 2-5 bit ADPCM data
- On line configurable compression rate between 40, 32, 24 and 16 kbits/s
- On line configurable for µ-law and A-law encoding or decoding on a channel to channel basis
- Burst and continuous mode operation
- Global and individual channel reset
- Coding of each data sample complete in 16 cycles
- Optimized for Virtex, Virtex-E and Spartan-II architectures
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a Xilinx AllianceCORE partner
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Implementation Example
| Target Device |
Virtex
XCV200-6
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Virtex-E
XCV200E-8
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Spartan II
XC2S150-6
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| Size |
1822 Slices
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1804 Slices
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1728 Slices
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| Speed |
16.6 MHz
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21.3 MHz
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17.8 MHz
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Obtainable without stringent place and route constraints
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Ordering information
| Part number |
Product Description |
Supported Devices |
| DO-DI-ADPCM32 |
32-Channel ADPCM Codec Core |
Virtex, Virtex-E, Spartan-II |
Please contact your local Xilinx Sales Office
for pricing information or to place an order. Xilinx LogiCORE ADPCM products
are provided as a single-use license under the  Xilinx
Core Project License agreement.
Additional Information
 to view the PDF files on this page.
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