SAN JOSE, Calif., August 3, 1998–Xilinx Inc., (NASDAQ:XLNX) today announced the new version of the Alliance Series software, version 1.5, expanding the performance and timing-driven compile time leadership by delivering 50 percent faster compile times and a 30 percent increase in the average clock speed for programmable logic devices. The new software version provides an HDL design solution tightly integrated into the designer's choice in EDA environments. HDL designers will achieve up to 155 MHz in design performance improvement with the new graphical constraints editor, higher clock speed from premier synthesis partners, Xilinx CORE Generator tool, floorplanner capabilities, and performance enhancements to the implementation tools. This is the first programmable logic production release software to support the industry's first million-gate FPGA, available from Xilinx later this year. 

"In this latest release, we have taken programmable logic solutions beyond the traditional areas of performance, productivity, and ease-of-use," said Carol Fields, Xilinx Alliance Series product line manager. "We have redefined density leadership by adding new features, aiding the expansion of FPGAs into the ASIC market. Xilinx has worked closely with our EDA partners to co-define, develop, and document the next generation of design methodologies." 

New AKAspeed Technology 

A key element in the 1.5 release is the delivery of the new Xilinx AKAspeed technology, a suite of new algorithms and algorithmic strategies combined with advanced new feature sets and applications optimized to address the elements of today's higher performance, higher density designs. Both mainstream and power users can leverage the benefits of this new technology. AKAspeed technology provides minimum timing delays, voltage and temperature prorating, graphical constraints editor, and enhancements to the existing technology elements such as timing driven implementation, K-paths, 

advanced timing analysis algorithms, robust constraints language, and incremental design capabilities and the Industry's most complete intellectual property strategy. 

New Addition of Floorplanner Capabilities 

The Xilinx graphical floorplanner allows the designer's knowledge of the structure of the design to be added to the implementation of the design increasing the designs performance by as much as 40 percent. 

Minimum Delays, Voltage and Temperature Pro-Rating 

With the latest version of the Alliance software, designers can test their designs under maximum and minimum timing conditions. Minimum delay guarantees functionality of designs with asynchronous circuits frequently found in complex digital products. Voltage and temperature pro-rating factors—never before available for SRAM-based silicon designs - allow the design to be tested under more favorable operating conditions. Designers can achieve speed enhancements proportional to the percentage change in either voltage or temperature, achieving higher clock speeds for maximum delay specifications. These new faster delays can be evaluated using static timing analysis tools and simulation. 

Graphical Constraints Editor 

The new graphical constraints editor helps guide users to the optimum constraints setting, shortens the learning curve, and enhances ease-of-use by displaying the clocks and ports in the design in a spreadsheet format. Users will reach desired design performance in the first pass. The constraints editor eliminates having to know the names of nets and components and predefined groups of logic elements such as I/O, registers, latches, memory, clocks, and clock enables. 

HDL Simulation 

FPGA designers are adopting an HDL verification methodology to help detect errors early in the design cycle. The cost of fixing an error grows exponentially as the design cycle progresses. Simulation detects problems quickly, allowing designers to observe internal nodes in critical paths versus hardware debugging, which is much slower. A "testbench" strategy allows for parallel development of board-level and system firmware testing with the implementation of the FPGA. Designers have seen a 25 percent reduction in the design cycle time using HDL testbench strategy, allowing new products to be released two to six months sooner. The latest Alliance Series 1.5 release provides two new design guides for the industry's leading HDL simulators and high quality results with tight integration. Xilinx utilizes industry standard interfaces such as Vital, Verilog and SDF, allowing the necessary enhancements to fit seamlessly into existing design flows including the ability to simulate the unique global set/reset capability of FPGAs without modifying the testbench. 

Other 1.5 Performance and Productivity Features 

The latest release of the Xilinx CORE Generator tool, announced earlier this year, ships in the 1.5 release and provides designers access to high performance LogiCORE and AllianceCORE products such as PCI, DSP, microprocessor, and USB cores. The 1.5 release is "year 2000" compliant; the software internally processes years as a full four-digit number but displays it in the two-digit format. 

Xilinx EDA partners such as Aldec, Cadence, Exemplar Logic, OrCAD, Model Technology, Mentor Graphics, Metamor, Synplicity, Synopsys, Veribest, and Viewlogic contributed to the 20 percent faster run times, system performance enhancements, and easier mixed-EDA vendor support in the 1.5 version software. 

The Alliance Series 1.5 software provides architecture-specific device support for all Xilinx product families, including XC4000X, XC4000XV, XC3100A/L, XC5200, and Spartan/XL FPGAs, plus XC9500 CPLDs. It will also support the Virtex series available later this year. The new software is available for popular PC and workstation platforms and operating systems such as Windows95 and Windows NT; Chinese, Korean, and Japanese Windows; Solaris and HP-UX. The new Alliance Series software pricing starts at $95 on PCs and $750 on workstations. Evaluation software is free. 

Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented field programmable gate arrays (FPGA) and commands more than half of the world market for these devices today. Xilinx solutions enable customers to significantly reduce the time required to develop products for the computer, peripheral, telecommunication, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com.