Cadence Interface - Documentation

Concept-HDL Design Flow

• Concept-HDL - New Standard in Schematic Capture
• Integrate FPGA & System Design Using Concept HDL

Verilog

• XAPP108: HDL Simulation Using the Xilinx Alliance Series Software , 05/2000
  Application Note describing the basic flow and issues to be aware of when performing HDL simulation of a Xilinx device using a Verilog or VHDL simulator.
• Synthesis and Simulation Design Guide, 4/98 (1.3 MB)
  Manual providing a general overview for designing into FPGAs using VHDL and Verilog.