Mentor Graphics Interface: Glossary of Terms AMPLE API component component interface Component Interface Browser (CIB) Convert Design cross-probing DDMS Design Architect Design Data Port (DDP) Design Viewpoint Editor (DVE) EDDM EDDM single object EDIF ENRead ENWrite Falcon Framework FlexSim Gen_sch8 HDL IEEE location map LogiBLOX model registry ModelSim QuickHDL QuickHDL Pro QuickSim Unisim Verilog VHDL VHSIC viewpoint VITAL X-BLOX XBLXGS XNF AMPLE Advanced Multi-Purpose Language. Mentor's scripting language, used by Falcon Framework programs such as Design Architect, Design Viewpoint Editor, and QuickSim. API Applications Programming Interface. A set of software libraries, developed by a particular software vendor, that allows outside software programs to interface with programs from that vendor. component The highest-level Mentor object, which may contain schematics, EDDM single objects, symbols, and design viewpoints. Roughly equivalent to an entity construct in VHDL. Recognizable as a comp_name directory along with a comp_name.mgc_component.attr file. component interface A description of how a Mentor component interfaces with upper-level hierarchy. A port description with a model registry, roughly equivalent to an entity port listing (along with architecture declarations) in VHDL. Component Interface Browser (CIB) A program that allows a designer to view and edit a component interface. In most cases, this is done to add or remove models from a component's model registry. Convert Design A utility within the Xilinx-specific version of Design Architect used to retarget a schematic to a new device family. cross-probing Interprocess communication between QuickSim and DVE that allows simulation results from a post-route netlist to be annotated visually to a pre-route schematic DDMS Design Data Management System. Mentor's file/object-management system. Design Architect (DA) Mentor's schematic editor. Design Data Port (DDP) An API that allows third-party software to interface with Mentor model-generation programs. Design Viewpoint Editor (DVE) A tool which allows a designer to edit design viewpoints. EDDM Electronic Design Data Model. Mentor's proprietary netlist format. Comes in two major flavors: schematic object and single object. EDDM single object A circuit model based on Mentor's connectivity (non-graphical) netlist format. Recognizable as a set of files with a model.Eddm_single_object.attr file and one or more model.sobj_n files. EDIF Electronic Design Interchange Format. An industry-standard netlist format. ENRead Mentor's EDIF netlist reader, translates an EDIF netlist into an EDDM single object. ENWrite Mentor's EDIF netlist writer, translates EDDM into EDIF. Falcon Framework The common GUI and file/object-management system used by the majority of Mentor programs. Also refers to the API that interfaces with the Falcon Framework. FlexSim The name given to the communications backplane between QuickSim and QuickHDL when running under the control of QuickHDL Pro. Allows QuickSim and QuickHDL to talk to each other, resulting in a seamless integrated simulation between schematic and HDL. Gen_sch8 (pronounced "Jen Skate") A program that ships with the Mentor interface (5.x) that translates an XNF file into a (quite non-aesthetic) Mentor schematic object. See also XBLXGS. HDL Hardware Description Language. A language which describes circuits in textual code. The two most widely accepted HDLs are VHDL and Verilog. IEEE (pronounced "I triple-E") Institute of Electrical and Electronics Engineers. location map (a.k.a. "MGC location map") A text file that lists "soft names" (a.k.a. variables) that Mentor tools use to resolve relative directory paths (e.g., "$LCA/xc4000x/ram16x1"). For an example of a location-map file, see the Xilinx-Mentor Getting Started page. LogiBLOX The M1 incarnation of Blocks of Logic Optimized for Xilinx, a module-synthesis tool that allows generation of architecture-optimized functions such as counters, adders, and data registers. model registry A list (which may include schematics, EDDM single objects, and symbols) which identifies what models can be used to describe a component. ModelSim Model Technology's upcoming VHDL/Verilog simulator, consolidating MTI's V-System and Mentor Graphics' QuickHDL simulators. QuickHDL Mentor's VHDL/Verilog simulator, written using an API linked to Model Technology's HDL simulation core. QuickHDL Pro Mentor's co-simulation utility that allows mixed schematic and HDL designs to be simulated in a single, integrated environment. QuickSim and QuickHDL are run concurrently, and communicate with each other across a FlexSim backplane. QuickSim Mentor's schematic/EDDM simulator. Unisim A VHDL/Verilog-based library that allows behavioral simulation of instantiated Unified-library components in QuickHDL or ModelSim. Verilog An industry-standard HDL developed by Cadence Design Systems. Recognizable as a file with a .v extension. VHDL VHSIC Hardware Description Language. An industry-standard (IEEE 1076.1) HDL. Recognizable as a file with a .vhd or .vhdl extension. VHSIC Very High Speed Integrated Circuit. viewpoint (a.k.a. "design viewpoint") An object which tells Mentor software programs how to interpret or process a design component. Recognizable as a vpt_name directory along with a vpt_name.Eddm_design_viewpoint.attr file and one or more vpt_name.dvpt_n files. Viewpoints are roughly analogous to eyeglasses; as with eyeglasses, different viewpoints can affect the way in which the software sees a design. For example, the Xilinx XNF viewpoint describes what types of Xilinx components are primitives, preventing ENWrite from writing out simulation models in its output EDIF file. Using multiple board-level simulation viewpoints (like those used for Xilinx Solution 619) allows a designer to quickly switch between simulating functional and timing models, while still running QuickSim on the same board-level schematic. Roughly equivalent to a configuration in VHDL. VITAL VHDL Initiative Toward ASIC Libraries. A VHDL-library standard (IEEE 1076.4) that defines standard constructs for simulation modeling, accelerating and improving the performance of VHDL simulators. X-BLOX Blocks of Logic Optimized for Xilinx. A schematic-based synthesis tool where generic bus-width-independent symbols such as counters, adders, and data registers are used to implement architecture-optimized functions. XBLXGS [sic] X-BLOX Generate Schematic. Generates a "clone" schematic model from an X-BLOX schematic underneath the simdir subdirectory. Roughly equivalent to XDraw in the Viewlogic simulation flow. Uses Gen_sch8 to generate simulation models for X-BLOX modules. XNF Xilinx Netlist Format.