Synopsys FPGA Compiler Interface Journal - Documentation

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Current Release - Alliance Series 3.1i

• Manuals
• Application Notes
• Articles

Older Release - XACT 5.X

• Manuals
• Articles

Alliance Series Software:

Manuals
 
• Alliance 3.1i Software Documentation

 
• Alliance 2.1i Software Documentation

 
• XSI Synopsys Interface and Tutorial Guide, version 1.5, 8/98 (861 kB) 

This is a PDF version of the Dynatext manual for using the Synopsys FPGA Compiler, Design Compiler and VSS simulator with the Xilinx Alliance series version 1.5i.
 
• Synopsys (XSI) Synthesis and Simulation Design Guide, 4/98 (1.4 MB)

This is a manual to assist Synopsys FPGA Compiler users to design into FPGAs using the M1 software. This manual includes design hints (Verilog and VHDL), synthesis tips and simulation techniques

The following files are to accompany this manual:
 

• m1_xsi_hdl.tar.Z, 5/98 (13.0 MB)
• m1_xsi_hdl.zip, 5/98 (7.7 MB)

Verilog and VHDL example files to accompany the Synopsys (XSI) Synthesis and Simulation Design Guide (for M1). File contains all VHDL and Verilog source, script and design files.
• m1_xsi_verilog.tar.Z, 5/98 (5.1 MB)
• m1_xsi_verilog.zip, 5/98 (5.1 MB)

Verilog example files to accompany the Synopsys (XSI) Synthesis and Simulation Design Guide (for M1). File contains all Verilog source, script and design files.
• m1_xsi_vhdl.tar.Z, 5/98 (6.2 MB)
• m1_xsi_vhdl.zip, 5/98 (4.2 MB)

VHDL example files to accompany the Synopsys (XSI) Synthesis and Simulation Design Guide (for M1). File contains all VHDL source, script and design files.
 
• The Quick Start Guide for Xilinx Alliance Series 1.5., 11/98 (597 kB)

This guide provides an overview of M1.5 software, installation, an Implementation Tools Tutorial, Interface Notes, and software features. This guide also includes an Alliance Constraints section.
See Appendix D of this manual for information specific to Synopsys FPGA/Design Compiler.

Application Notes
 
• XAPP107: Synopsys/Xilinx High Density Design Methodology Using FPGA Compiler 8/98 (255 kB) 

Xilinx and Synopsys authored a high density design application note. This application note was designed to help users to implement 100,000+ gate designs in 4000X FPGAs, using FPGA Compiler I. This application note goes over a variety of techniques, strategies, and tools to assist in implementing 100,000+ gate designs.

The following file is to accompany the application note:
 

• makeucf.tar.Z, 8/98 (3 kB)

Makeucf is a Perl script that was designed to replace maketnm/addtnm from the older XACT software. This script can be used with an FPGA Compiler netlist targeting an XC4000X family device to make a UCF file for constraining the design.
 
• XAPP108: Chip-Level HDL Simulation Using the Xilinx Alliance Series, 5/98 (200 kB)

Application Note describing the basic flow and issues to be aware of when performing a chip-level simulation of a Xilinx device using a Verilog or VHDL simulator and the Xilinx Alliance 1.4 release.
 
• XAPP105: A CPLD VHDL Introduction, 2/98 (60 kB)

This application notes covers the basics of VHDL as applied to Complex Programmable Devices (CPLDs).

Articles
 
• XCELL  Q1 00: FPGA System Simulation and Synthesis, 1/00 (155 kB)

This XCELL article discusses synthesis using FPGA Compiler II and simulation using VCS.
 
• XCELL  Q3 99: New FPGA Compiler II - For Million-Gate Designs, 4/99 (135 kB)

Implement ASIC compatible flows for million-gate FPGAs.
 
• XCELL  Q1 99: HDL Advisor - Creating the Most Efficient Comparators, 1/99 (329 kB)

This XCELL article discusses efficient coding styles for comparators.
 
• XCELL Q4 98: HDL Advisor: Using Nested If Statements, 10/98 (236 kB)

Improper use of the "Nested If" statement can result in increased area and longer delays.
 
• XCELL Q3 98: FPGA Design Cycle Time Reduction and Optimization, 7/98 (68 kB)

This XCELL article discusses a synthesis technique used to reduce the design cycle time.
 
• XCELL Q3 98: Using Synopsys SmartModel FPGA Models to Verify Xilinx FPGA Designs, 7/98 (250 kB)

This XCELL article shows the advantages and basic flow for using Synopsys SmartMODEL with FPGA designs.
 
• XCELL Q1 98: New UNISIM Libraries for Functional VHDL and Verilog Simulations, 1/98 (135 kB)

This XCELL article briefly explains the new functional simulation libraries added in the A1.4 release.

Manuals
 
• Synopsys (XSI) For FPGAs Interface/Tutorials Guide 7/95 (1.6 MB)

Xilinx-Synopsys manual for targeting FPGAs with the XACT 5.X release of software.
 
• XACTstep Version 5.2/6.0 Synopsys Release Notes 7/95 (149 kB)

Release Notes for the Xilinx-Synopsys Interface release version 5.2.
 
• HDL Synthesis For FPGAs Design Guide 8/95 (2.2 MB)

Synthesis tips and techniques for XACT-Synopsys users.

The following files are to accompany this manual:
 

• xsi_files.tar.Z, 6/95 (83 kB)

Tactical code, XNF files for RPMs and a default Synopsys setup file to accompany the HDL Synthesis Guide.
• xsi_verilog.tar.Z, 6/95 (3.0 MB)

Verilog Examples from HDL Synthesis for FPGAs Design Guide.
• xsi_vhdl_no_wk.tar.Z, 6/95 (5.1 MB)

VHDL Examples with SIM, SYN and MRA files in Work directory.
• xsi_vhdl_no_wk.tar.Z, 6/95 (3.2 MB)

VHDL Examples without SIM, SYN and MRA files in Work directory
 
• CPLD XSI Design Guide 2/96 (549 kB)

XACT-CPLD and Synopsys interface manual for targeting CPLD (9500 family) devices.
Synthesis tips and techniques for XACT-Synopsys users.
 
• Synopsys (XSI) For EPLDs Interface/Tutorials Guide 7/95 (682 kB)

XACT-EPLD and Synopsys interface manual for targeting EPLD (7200 and 7300 families) devices.

Articles
 
• XCELL Q2 96: HDL Synthesis and Built-In Clock Enables, 6/96 (21 kB)

This XCELL article discusses how to code for the use of the built-in clock enables for Xilinx FPGAs.