Xilinx Virtex FPGA: Top Solutions  To access our full database of Xilinx Solutions, please consult our Answers Search.   Hot Solutions Solution 2586 - 2.1i: CE/Timing: VIRTEX CLKDLL TIMING for 2.1i. Solution 6905 - Virtex: How to apply a Period constraint on Virtex CLKDLL for 2.1i. Solution 5048 - Synopsys, Virtex: replace_fpga and uniquify should not be used during synthesis using FPGA/Design Compiler (NGDHelpers 406) Solution 6110 - Virtex: What are the differences between Vref(R) and Vref(r) in the package drawings. Solution 6214 - Virtex IOFF: How to use the registers/FFS in the IOB? Solution 6362 - Virtex CLKDLL HDL simulation: LOCKED signal doesn't lock if it's not in ps time resolution. Solution 7822 - How to infer SRL16 for Virtex/E devices in HDL (Verilog/VHDL)? (in EXEMPLAR and SYNPLIFY) Solution 8005 - Virtex-E CLKDLL: How to create 4X clock using VirtexE CLKDLLs. Solution 8006 - Virtex-E CLKDLL: What are the input clock frequency range for VirtexE CLKDLLs. Solution 8187 - Virtex-E LVDS: How to use LVDS IOSTANDARD in VirtexE. Solution 8202 - Virtex-E FPGA Express 3.3: How to instantiate special Virtex-E I/O standards (LVDS, LVPECL). Solution 7880 - Virtex-E: Are the Virtex-E I/O pins 5V compatible?