This version is in Word 97 format, and it includes a
number of new constraints related to clocks and
buffer trees.
The new constraints cover
- jitter as part of the waveform description,
rather than part of clock uncertainty
- a frequency divisor option for Derived Waveform,
to keep the relationship between the parent and
derived waveforms based on integers or rational
ratios
- external insertion delays (outside the current
design) that affect the arrival time of the clock
edges at a clock root: Clock Arrival
- the delay of the common portion of external insertion
delays leading to two clock roots, for common pessimism
removal: Common Insertion Delay
- the relationship between a master clock root and a
derived clock root for automatically calculating
phase shift through a multiplier or divider:
Derived Clock
- target-based clock uncertainty versus inter-clock
uncertainty
- changes to the parameters for Clock Delay. Removed
the ability to specify skew between explicit leaf pins,
as well as the source latency (now specified with
Clock Arrival in a more general way). Added a Data
leaf parameter to indicate leaf pins that are on the
boundary between clock and data networks (for example,
when a clock signal is used to gate data signals, rather
than the other way round). Register clock input pins
don't count as Data leaves.
- insertion delay, skew, and slew for general buffer
trees: Tree Delay
- default mode for analysis of general buffer trees:
Tree Mode
This version doesn't include Steve Grout's updates to the
parasitics, pending a new version based on Greg and Steve's
discussion.
Thanks,
Mark