Re: [$ieee-1850] Assertion-Control System Tasks

ben,

>SystemVerilog Assertions has Assertion-Control System Tasks to enable
>/ disable the turning ON /OFF of assertions. This is very useful.
>PSL does not have that feature.
>Do we want to add this feature?

maybe, once we have made the decision to define the embedding of psl within
an hdl. until the embedding of psl within an hdl is defined in the
standard, the question is meaningless - where would such controls go?

cindy.

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Cindy Eisner
Formal Methods Group
IBM Haifa Research Laboratory
Haifa 31905, Israel
Tel: +972-4-8296-266
Fax: +972-4-8296-114
e-mail: eisner@il.ibm.com

ben cohen <hdlcohen@gmail.com>@eda.org on 13/11/2004 00:59:30

Please respond to ben cohen <hdlcohen@gmail.com>

Sent by: owner-ieee-1850@eda.org

To: ieee-1850@eda.org
cc:
Subject: [$ieee-1850] Assertion-Control System Tasks

SystemVerilog Assertions has Assertion-Control System Tasks to enable
/ disable the turning ON /OFF of assertions. This is very useful.
PSL does not have that feature.
Do we want to add this feature?

In SystemVerilog:
assert_control_task ::= assert_task [ ( levels [ ,
list_of_modules_or_assertions ] ) ] ;
assert_task ::=
               $asserton
              | $assertoff
              | $assertkill

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Received on Mon Nov 15 04:25:22 2004