Re: [$ieee-1850] Assertion-Control System Tasks

Cindy,
Considering the vunit, we can define a set of reserved procedures or
tasks called "asserton, assertoff, assertkill". We could also state
that they would have significance only in simulation. Currently a
user can either use the vunit, or puts PSL within HDL as comments, and
vendors have adopted the pragma "psl". I see no reason why this
cannot be maintained. For example:
module testbench;
....
always @ (posedge clk) begin
     if(in_setup_mode)
         // psl assertoff;
     else if (done_setup_mode)
         // psl asserton;
end
endmodule

On Mon, 15 Nov 2004 10:52:31 +0200, Cindy Eisner <eisner@il.ibm.com> wrote:
>
>
> ben,
>
> >SystemVerilog Assertions has Assertion-Control System Tasks to enable
> >/ disable the turning ON /OFF of assertions. This is very useful.
> >PSL does not have that feature.
> >Do we want to add this feature?
>
> maybe, once we have made the decision to define the embedding of psl within
> an hdl. until the embedding of psl within an hdl is defined in the
> standard, the question is meaningless - where would such controls go?
>
> cindy.
>
> --------------------------------------------------------------------
> Cindy Eisner
> Formal Methods Group
> IBM Haifa Research Laboratory
> Haifa 31905, Israel
> Tel: +972-4-8296-266
> Fax: +972-4-8296-114
> e-mail: eisner@il.ibm.com
>
> ben cohen <hdlcohen@gmail.com>@eda.org on 13/11/2004 00:59:30
>
> Please respond to ben cohen <hdlcohen@gmail.com>
>
> Sent by: owner-ieee-1850@eda.org
>
>
> To: ieee-1850@eda.org
> cc:
>
>
> Subject: [$ieee-1850] Assertion-Control System Tasks
>
> SystemVerilog Assertions has Assertion-Control System Tasks to enable
> / disable the turning ON /OFF of assertions. This is very useful.
> PSL does not have that feature.
> Do we want to add this feature?
>
> In SystemVerilog:
> assert_control_task ::= assert_task [ ( levels [ ,
> list_of_modules_or_assertions ] ) ] ;
> assert_task ::=
> $asserton
> | $assertoff
> | $assertkill
>
> --------------------------------------------------------------------------
> Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
> http://www.vhdlcohen.com/ vhdlcohen@aol.com
> Upcoming book: SystemVerilog Assertions Handbook, ISBN 0-9705394-7-9
>
> Author of following textbooks:
> * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition,
> 2004 isbn 0-9705394-6-0
> * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
> 0-9705394-2-8
> * Component Design by Example ", 2001 isbn 0-9705394-0-1
> * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
> 0-7923-8474-1
> * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
> ---------------------------------------------------------------------------
Received on Mon Nov 15 08:47:31 2004