Re: Comment on IR2125

All,
 > In IR2125, Jim suggests changing the resolution function in std_logic-1164
 > so that 'Z' and '-' resolve to '-' rather than 'X'.
 >
 > To aid our discussion tomorrow, here's an excerpt from IEEE 1165-1993:
 >
 >   A.8 Modeling with don't care's
 >
 >   A.8.1 Use of the don't care state in synthesis models
 >
 >   For synthesis, a VHDL program is a specification of the
 >   functionality of a design.

The heart of this issue is that these types are used
for testbenches as well as synthesis, yet the rationale
focuses on synthesis.

In my testbench, for some tests, some pieces of the results
are to be ignored.  The result values are std_logic and
std_logic_vector.  When checking expected values with
received values, it is natural to want to use the value
'-' as don't care as that is what std_logic_1164 suggests
that '-' means.  This is especially nice as in the response
checker, std_match can be used.

The testbench uses records as channels to communicate test
values between models.  The records are multiply driven since
they are inout of more than one entity.  As a result, the
records execute the resolved resolution function for std_logic.
Unfortunately, when 'Z' and '-' are driven, 'X' is the resolved
result.

As a result, I have to write a special comparison that treats
an 'X' in the expected value as a don't care.  Yikes.

What really bugs me is that std_logic_1164 leads one to believe
that '-' is don't care, however, the only time it means don't
care is when you do either:
   Y <= '-' ;

or
   if std_match(A_slv4, "11--") then


Otherwise it is just a glorified 'X'.

Jim

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Jim Lewis
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