RE: ISAC: Vote on IR2128 and review IR2126

From: Peter Ashenden <peter_at_.....>
Date: Wed Feb 20 2008 - 17:38:58 PST
Jim,

By tabling the IR, we would miss the opportunity to correct the oversight of
not including generate declarative regions as places where a variable must
be shared. Can we divide the question?

Cheers,

PA

--
Dr. Peter J. Ashenden         peter@ashenden.com.au
Ashenden Designs Pty. Ltd.    www.ashenden.com.au
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> -----Original Message-----
> From: owner-isac@server.eda.org 
> [mailto:owner-isac@server.eda.org] On Behalf Of Jim Lewis
> Sent: Thursday, 21 February 2008 12:02
> To: Chuck Swart - MTI
> Cc: isac@server.eda.org
> Subject: Re: ISAC: Vote on IR2128 and review IR2126
> 
> 
> Chuck,
> I vote to table 2128.
> 
> Accellera should have approved D4.0 and we have plenty of 
> higher priority stuff for 1076-2008.
> 
> I think the analysis is correct WRT block_declarative_part 
> being exactly a concurrent_declarative_part, however, the 
> following appear to be the same:
>    section 2.2 subprogram_declarative_part,
>    section 3.5.2 protected_type_body_declarative_part
>    section 9.2 process_declarative_part
> 
> If I am right, we may wish to consolidate, but I would place 
> this at a low priority and would not see it being added to 1076-2008.
> 
> Jim
> 
> > I know that we're all busy, but we need everyone to vote on IR 2128 
> > and review IR 2126. In my opinion, IR 2128 is pretty 
> straightforward. 
> > I need feedback on IR 2126, so that I can make any needed 
> revisions by 
> > the next meeting.
> > 
> > Hopefully after tomorrow Accellera will pass D4.0 over to the IEEE, 
> > and the clock will start ticking for final revisions.  This is 
> > definitely the time to move on all your action items.
> > 
> > Chuck Swart
> > 
> > 
> 
> 
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> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Jim Lewis
> Director of Training             mailto:Jim@SynthWorks.com
> SynthWorks Design Inc.           http://www.SynthWorks.com
> 1-503-590-4787
> 
> Expert VHDL Training for Hardware Design and Verification 
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Received on Wed Feb 20 17:49:32 2008

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