IM18: Clock ID 0

ITC Team,

Here's my action item from the 4-8-04 meeting regarding IM 18.

The committee agreed that if we tighten up the specification
to use "emergency brake" clock stoppage semantics the need for
reserving clock ID=0 becomes moot.

The term "emergency brake" refers to stoppage of all clocks -
fast and slow - immediately if ReadyForCclock is deasserted
or any clock - fast or slow.

This is in contrast to "just-in-time" semantics where all
clocks proceed advancing until the next edge of the particular
clock being stopped at which point all clocks stop - as is
currently in the specification.

The wording in section "5.1.5.2 Signals", under "ReadyForCclock"
on page 34 shall be revised as follows:

"ReadyForCclock
This input [...] to advance. One of the most useful [...] the DUT.
If this input to one of the SceMiClockControl instances associated
with a given controlled clock is deasserted, the next posedge of
all cclocks are immediately disabled. Even in reacting to a
ReadyForCclock deassertion of a slower clock, the infrastructure
shall immediately disable not only the next posedge of that slower
clock, but all posedges of all other faster clocks that occur
prior to that posedge."

Rewording for ReadyForCclockNegedge:

"ReadyForCclockNegEdge
Similarly, for negedge control, if this input to one of the
SceMiClockControl instances associated with a given controlled
clock is deasserted, the next negedge of all cclocks are
immediately disabled. Even in reacting to a ReadyForCclockNegEdge
deassertion of a slower clock, the infrastructure shall immediately
disable not only the next negedge of that slower clock, but all
negedges of all other faster clocks that occur prior to that negedge."

Support for [...]."

-- johnS

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Received on Tue Apr 27 12:52:21 2004