IM19: Instantiating the Clock macro

ITC Team,

Here's my action item from the 4-8-04 meeting regarding IM 19.

At Per's request, we decided to relax the criteria that
define how a module is to be regarded as transactor.

In the current specification it is tightly defined as any
module with a SceMiClockControl instantiated immediately
inside it (see section 5.2.1, page 35 under "Number of
transactors").

In the last meeting the committee agreed to expand this to
handle the case where a transactor does not excercise clock
control but can still be regarded as a transactor.

The wording in section 5.2.1 Parameters on page 35 shall be
revised as follows:

"Number of transactors
The number of transactors shall be derived by counting the number
of modules in the user’s design that qualify as transactors. Any one
of 3 conditions can qualify a module as a transactor:

1. The module has a SceMiClockControl macro instantiated immediately
     inside it, or,

2. The module has the following parameter defined within its scope:
     Verilog:
         parameter SceMiIsTransactor = 1;

     VHDL:
         generic( SceMiIsTransactor: boolean := true );

     or,

3. The module has at least one SceMi message port instantiated
     immediately inside it and neither that module nor any of its
     enclosing parent modules has otherwise been defined as a
     transactor.

Nested transactors are allowed. A message port's owning transactor
is defined to be the lowest module in that port's enclosing hierarchical
scope that qualifies as a transactor based on the definition above."

-- johnS

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Received on Tue Apr 27 12:52:33 2004