Issue IM14: Cycle stamp zeroing

From: Bojsen, Per <bojsen@zaiqtech.com>
Date: Tue Apr 27 2004 - 20:10:37 PDT

Hi,

here is my proposal for the wording to resolve issue IM14:

  The cycle stamp shall be zero while ureset is asserted and shall
  be 1 on the first rising edge of the implicit 1/1 cclock after
  ureset is deasserted.

This text can be inserted in the paragraph under the CycleStamp()
method declaration on the middle of p. 50 of the 1.0 revision of the
standard. I suggest inserting the text after the second sentence
of the paragraph.

Per 

-- 
Per Bojsen                                Email: <bojsen@zaiqtech.com>
Zaiq Technologies, Inc.                   WWW:   http://www.zaiqtech.com
78 Dragon Ct.                             Tel:   781 721 8229
Woburn, MA 01801                          Fax:   781 932 7488
Received on Tue Apr 27 20:10:47 2004

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