Shabtay,
That was indeed my intent. Thanks for catching this.
-- johnS
Shabtay Matalon wrote:
> John,
>
>
>
> I guess your intent was:
>
> If the user instantiates a 1/1 cclock without a don't care duty cycle, then
> that becomes the fastest clock in the system, although it limits
> performance
> to be only half as fast as the uclock, since in this case, both edges
> must be
> scheduled on posedges of uclock.
>
> I removed the ‘with’ before without. Please take a look.
>
>
>
> Shabtay
>
>
>
> ------------------------------------------------------------------------
>
> If the user instantiates a 1/1 cclock with without a don't care duty
> cycle, then
> that becomes the fastest clock in the system, although it limits
> performance
> to be only half as fast as the uclock, since in this case, both edges
> must be
> scheduled on posedges of uclock.
>
> The fastest cclock is also the basis for cycle stamping (see section
> 5.4.5.3 of
> scemi-108.pdf). The cyclestamp will always be the number of fastest cclock
> cycles since reset.
>
> In more complex systems that require multiple clocks ...
>
> --------------- end text ----------------------
>
> -- johnS
>
> ______________________________/\/ \ \
> John Stickley \ \ \
> Principal Engineer \ \________________
> Mentor Graphics - MED \_
> 17 E. Cedar Place \ john_stickley@mentor.com
> Ramsey, NJ 07446 \ Phone: (201) 818-2585
> ________________________________________________________________
>
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