(old)Verilog support

I want to correct (enhance?) Brian's comment in the minutes that everyone
agreed that option #3 (Verilog would not be supported) should be discarded.

I understand the simulation vendors need to be more conservative reg'd
closing a door that might be a problem somewhere in the customer base, but
my preference would be to take this route. This is just a preference; I
expect that some support for oldVerilog will become part of the Scemi2.0
spec, but at the very least, I would hope that it could become a less
pressing issue and not distract from (what I believe are) more higher
priority discusssions we should be having.

Without starting a resumption of the discussion about this matter
(hopefully), the main reasons for my position are this:
  * future IP written to SCEMI 2.0 compliance won't be written in
oldVerilog. To do so would mean the IP would need special libraries,
licenses, etc. to run in pure simulation mode. Pure simulation mode is the
default use model for IP.

  * users are phasing in SV rapidly. All 3 majors simulators offer some
level of support of SV, and that support is increasing rapidly. For most
users, there is SOMETHING in SV (whether it be assertions, RTL design
enhancements, DPI, etc.) that is giving them cause to use SV now rather than
later. Other users need to catch up.

The VHDL topic is separate, I won't go there.

I won't respond to any emails on this subject until most of the important
SSCMI 2.0 topics are discussed and resolved. 7:^)


---------------------------------------
---    Russ Vreeland (949)926-6143  ---
---    vreeland@broadcom.com        ---
---    Senior Principal Engineer    ---
---    Broadcom Corporation         ---
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