Re: (old)Verilog support

Hi Russ,

>   * users are phasing in SV rapidly. All 3 majors simulators offer some
> level of support of SV, and that support is increasing rapidly. For most
> users, there is SOMETHING in SV (whether it be assertions, RTL design
> enhancements, DPI, etc.) that is giving them cause to use SV now rather
> than
> later. Other users need to catch up.

In my mind there is more to the issue of whether `old Verilog' should
be supported than simulator support.  We have to consider tools such
as synthesis tools as well.  Some SCE-MI implementations depend on
third-party synthesis tools.  Some even support multiple synthesis
tools.  While I would expect synthesis tools to eventually support
SystemVerilog more or less, I would not be surprised if this support
would lag the simulators by several years.  For this reason, if I were
an IP vendor and I was planning on supporting emulation as well as
pure simulation, I would avoid using new SystemVerilog features and
restrict myself to the synthesizable subset of old Verilog that is
also a subset of SystemVerilog (mainly avoiding the use of new keywords
as identifiers).  This would give me the broadest compatibility.
End users may have further constraints that prevent the adoption
of SystemVerilog such as in-house tools that only understand
Verilog.  For these reasons I think we need to support Verilog at
least for a while.

However, I agree with you that we should move on to more important
issues and return to this later.

-- 
Per Bojsen                                Email: <bojsen@zaiqtech.com>
Zaiq Technologies, Inc.                   WWW:   http://www.zaiqtech.com
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