RE: Clarifying the Verilog and SV compatibility issue.

Hi Per,

[per wrote]

>One thing to keep in mind is that SCE-MI requires the infrastructure
>linker to be run on the HDL code.  The infrastructure linker would
>somehow know (the user probably tells it) what language the HDL is
>written in.  The infrastructure linker finds the exported/imported
>functions calls and replaces it with something the backend of the
>toolset can understand. 
[Shabtay] Correct. I just wanted to point out that the user MUST tell
infrastructure linker which code is written in Verilog and which code is
written in SV and that this issue could not simply be addressed by
simulation support of SV.

>Even if the bulk of the HDL code is to
>be considered old Verilog, you could still use the SystemVerilog DPI
>syntax for the function calls as the infrastructure linker will
>take care of them. 
[Shabtay] Correct.

>However, if the code uses new SystemVerilog
>keywords you would obviously not be able to run this code in a
>SystemVerilog simulator unchanged. 
[Shabtay] This sentence is not very clear to me. I hope what you meant
is that the code must be identified by the user as Verilog or SV code
for the simulator.

>In other words, SCE-MI 2.0
>models written in old Verilog will still need a third party
>SCE-MI 2.0 implementation to run on simulators regardless of
>whether we choose to support the attribute-based function calls
>or the DPI syntax (the latter being equivalent to not supporting
>old Verilog, more or less).
[Shabtay] Not only you would need a reference implementation, you will
need to provide the simulator the directive for each BFM or have it be
generated by the infrastructure linker. I don't have experience with non
Cadence simulators, but I would suspect that each vendor has their own
compile directives/switches with invocation syntax that varies from
simulator to simulator. I also don't know if the SV compile switch is
supported by all simulators.

Can one let me know if my "suspicion" is correct or not?