RE: Clarifying the Verilog and SV compatibility issue.

Hi Shabtay,

Per> However, if the code uses new SystemVerilog
Per> keywords you would obviously not be able to run this code in a
Per> SystemVerilog simulator unchanged.

Shabtay> This sentence is not very clear to me. I hope what
Shabtay> you meant is that the code must be identified by the user as
Shabtay> Verilog or SV code for the simulator.

No, what I was trying to point out is, if a user writing a
transactor for SCE-MI 2.0 is using old Verilog for the code
and SystemVerilog DPI for the interface to software, then
if the code uses one or more of the new SystemVerilog keywords
you could not run it on a SystemVerilog simulator despite
using DPI.  This was trying to show that it is not enough
to treat old Verilog as simply a proper SystemVerilog subset,
i.e., as SystemVerilog.  BTW, are there other incompatibilities
besides keywords?

Per

-- 
Per Bojsen                                Email: <bojsen@zaiqtech.com>
Zaiq Technologies, Inc.                   WWW:   http://www.zaiqtech.com
78 Dragon Ct.                             Tel:   781 721 8229
Woburn, MA 01801                          Fax:   781 932 7488