I took an action item to clarify the Verilog vs. SV backward compatibility issue. As indicated, I don't see a simulation support issue for the proposed data types, but a simple use model issue that we need to be aware of. SystemVerilog added new keywords into the language. Some users who wrote Verilog code simply used these keywords when writing Verilog 2001 for various uses as the obviously the SV keywords were not part of the Verilog language. The most common keywords that we have found in Verilog code are: do, priority, final, and bit. From a use model perspective, SV models/BFMs will have to be compiled in SV mode using a SV compiler directive (switch) while "old Verilog" will have to be compiled using the Verilog compiler, unless the Verilog code is searched for existence of new SV keywords and modified. If agreed, we need to table this as a use model assumption as we continue our discussion on data types. Shabtay SystemVerilog 3.0 added 36 new keywords -------------------------------------------------------------- always_comb always_ff always_latch assert bit break byte const continue do endinterface enum export extern forkjoin iff import int interface logic longint modport packed priority return shortint shortreal static struct timeprecision timeunit type typedef union unique void systemverilog 3.1 added 43 new keywords ------------------------------------------------------------- alias before bind chandle class clocking constraint context cover dist endclass endclocking endprogram endproperty endsequence extends final first_match inside intersect join_any join_none local new null program property protected pure rand randc ref sequence solve string super this throughout var virtual wait_order with ------------------------------------- Shabtay Matalon Solution Architect R&D, CVA Phone: (408) 428 5081 email: shabtay@cadence.comReceived on Wed, 24 Aug 2005 13:32:06 -0700
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